View EDR2518ABSE-AEP-E_1236005.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY DATA SHEET
288M bits Direct Rambus DRAM
EDR2518ABSE (512K words x 18 bits x 32s banks)
Description
The EDR2518AB (Direct RDRAM) is a general purpose high-performance memory device suitable for use in a broad range of applications including computer memory, graphics, video, and any other application where high bandwidth and low latency are required. The EDR2518AB is 1066MHz 288Mbits Direct Rambus DRAM (RDRAM), organized as 16M words by 18 bits. The use of Rambus Signaling Level (RSL) technology permits 800MHz to 1066MHz transfer rates while using conventional system and board design technologies. Direct RDRAM devices are capable of sustained data transfers at 0.9375ns per two bytes (7.5ns per sixteen bytes). The architecture of the Direct RDRAM devices allows the highest sustained bandwidth for multiple, simultaneous randomly addressed memory transactions. The separate control and data buses with independent row and column control yield over 95% bus efficiency. The Direct RDRAM devices 32 banks support up to four simultaneous transactions. System oriented features for mobile, graphics and large memory systems include power management, byte masking. It is offered in a CSP horizontal package suitable for desktop as well as low-profile add-in card and mobile applications. Direct RDRAM devices operate from a 2.5V supply.
Features
* Highest sustained bandwidth per DRAM device -- 2.1 GB/s sustained data transfer rate -- Separate control and data buses for maximized efficiency -- Separate row and column control buses for easy scheduling and highest performance -- 32 banks: four transactions can take place simultaneously at full bandwidth data rates * Low latency features -- Write buffer to reduce read latency -- 3 precharge mechanisms for controller flexibility -- Interleaved transactions * Advanced power management: -- Multiple low power states allows flexibility in power consumption versus time to active state -- Power-down self-refresh * Organization: 2K bytes pages and 32 banks, x 18 * Uses Rambus Signaling Level (RSL) for up to 1066MHz operation * FBGA ( BGA) package is Sn-Pb or lead free solder (Sn-Ag-Cu)
Document No. E0260E40 (Ver. 4.0) Date Published April 2003 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2002-2003
EDR2518ABSE
Ordering Information
Part number EDR2518ABSE-AEP EDR2518ABSE-AE EDR2518ABSE-AD EDR2518ABSE-8C EDR2518ABSE-AEP-E EDR2518ABSE-AE-E EDR2518ABSE-AD-E EDR2518ABSE-8C-E Organization* words x bits x Internal Banks 512K x 18 x 32s Clock frequency MHz (max.) 1066 1066 1066 800 1066 1066 1066 800 /RAS access time (ns) 32 (-32P) 32 (-32) 35 40 32 (-32P) 32 (-32) 35 40 Package 80-ball FBGA (BGA)
Note: The "32s" designation indicates that this RDRAM core is composed of 32 banks which use a "split" bank architecture
Part Number
E D R 25 18 A B SE - AEP - E
Elpida Memory Type D: Monolithic Device Product Code R: RDRAM Density & Bit Organization 2518: 288M (x18 bit) Environment Code Blank: Sn-Pb Solder E: Lead Free Speed AEP: 1066MHz (tRAC= 32ns, tDAC= 3clocks) AE: 1066MHz (tRAC= 32ns) AD: 1066MHz (tRAC= 35ns) 8C: 800MHz (tRAC= 40ns)
Package SE: FBGA (BGA with back cover)
Voltage, Interface A: 2.5V, RSL Die Rev.
2
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
Pin Configuration
80-ball FBGA ( BGA) Top View
10 9 8 7 6 5 4 3 2 1
O O O O O
O O O O O O O O O O O O O O O O O O O O O O O O O O O
O O O
O O O O O
O O
O O O B
O O O C
O O
O O
O O
O O
O O
O O
O O
O O
O O
O O
O O
O O
O O O S
O O O T
O O
A
D
E
F
G
H
J
K
L
M
N
P
R
U
10 9 8 7 6 5 4 3 2 1 A
GND GND
VDD
GND
GND
VDD
VDD
DQA8
CMD DQA7
VDD
DQA5
GND DQA3
GNDa DQA1
GNDa CTMN
VDD
CTM
VDD
GND
GND COL3
VDD
COL1
VDD
DQB1
GND DQB3
GND DQB5
VCMOS DQB7
VDD
DQB8
GND
VDD
ROW2 ROW0
VDD
GND GND
DQA6 SCK
DQA4
DQA2
DQA0
CFM GND
CFMN
ROW1 VREF
COL4 GND
COL2
COL0 GND
DQB0 GND
DQB2
DQB4 SIO0
DQB6 SIO1
GND GND
GND
VDD
VCMOS GND
VDD
VDDa
VDD
VDD
VDD
VDD
GND
GND
VDD
B
C
D
E
F
G
H
J
K
L
M
N
P
R
S
T
U
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Preliminary Data Sheet E0260E40 (Ver. 4.0)
3
EDR2518ABSE
Pin Description
Signal SIO0, SIO1 Input / Output Type
Note1
#pins 2
Description Serial input/output. Pins for reading from and writing to the control registers using a serial access protocol. Also used for power management.
Input / Output CMOS
CMD
Input
CMOS Note1
1
Command input. Pins used in conjunction with SIO0 and SIO1 for reading from and writing to the control registers. Also used for power management.
SCK
Input
CMOS
Note1
1
Serial clock input. Clock source used for reading from and writing to the control registers.
VDD VDDa VCMOS GND GNDa DQA8..DQA0 Input / Output RSL
Note2
18 1 2 22 2 9
Supply voltage for the RDRAM core and interface logic. Supply voltage for the RDRAM analog circuitry. Supply voltage for CMOS input/output pins. Ground reference for RDRAM core and interface. Ground reference for RDRAM analog circuitry. Data byte A. Nine pins which carry a byte of read or write data between the Channel and the RDRAM.
CFM
Input
RSL
Note2
1
Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity.
CFMN
Input
RSL
Note2
1
Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity.
VREF CTMN Input RSL
Note2
1 1
Logic threshold reference voltage for RSL signals. Clock to master. Interface clock used for transmitting RSL signals to the Channel. Negative polarity.
CTM
Input
RSL Note2
1
Clock to master. Interface clock used for transmitting RSL signals to the Channel. Positive polarity.
ROW2..ROW0
Input
RSL Note2
3
Row access control. Three pins containing control and address information for row accesses.
COL4..COL0
Input
RSL
Note2
5
Column access control. Five pins containing control and address information for column accesses.
DQB8..DQB0
Input / Output
RSL
Note2
9
Data byte B. Nine pins which carry a byte of read or write data between the Channel and the RDRAM.
Total pin count per package
80
Notes 1. All CMOS signals are high-true ; a high voltage is a logic one and a low voltage is logic zero. 2. All RSL signals are low-true ; a low voltage is a logic one and a high voltage is logic zero.
4
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
Block Diagram
RQ7..RQ5 or ROW2..ROW0
3 RCLK
DQB8..DQB0
9
CTM CTMN SCK, CMD SIO0, SIO1
2 2
CFM CFMN
RQ4..RQ0 or COL4..COL0
5
DQA8..DQA0
9 RCLK
1:8 Demux
TCLK RCLK
1:8 Demux
Packet Decode ROWR ROWA
11 ROP AV 5 DR 5 BR 9 R
Control Registers COLX
6 5 5
Packet Decode COLC
5 5 5 7
COLM
8 8
REFR
Power Modes
DEVID
XOP M
DX
BX
COP S
DC
BC
C
MB
MA
Match DM
Mux Row Decode PRER ACT
Match XOP Decode PREX
Match
Write Buffer Mux Mux
Column Decode & Mask Sense Amp 64x72
DRAM Core
64x72
SAmp SAmp 0/1 0
PREC 512x128x144 64x72
SAmp SAmp 0/1 0
RD, WR
72
Internal DQB Data Path
72
Bank 0 Bank 1 Bank 2
Internal DQA Data Path
72
72
SAmp 1/2
SAmp 1/2
RCLK
9
9
* * *
SAmp 13/14
* * *
Bank 13 Bank 14 Bank 15
* * *
SAmp 13/14
9
9
RCLK
Write Buffer
Write Buffer
1:8 Demux
1:8 Demux
SAmp 14/15
9
9
SAmp 14/15
SAmp 15
SAmp 15
SAmp 16
SAmp 16
SAmp 16/17
Bank 16 Bank 17 Bank 18
SAmp 16/17
TCLK
9
9
TCLK
SAmp 17/18
SAmp 17/18
9
8:1 Mux
* * *
SAmp 29/30
* * *
Bank 29 Bank 30 Bank 31
* * *
SAmp 29/30 SAmp SAmp 30/31 31
8:1 Mux
9
SAmp SAmp 30/31 31
Preliminary Data Sheet E0260E40 (Ver. 4.0)
5
EDR2518ABSE
CONTENTS
1. General Description................................................................................................................................................. 8 2. Packet Format ........................................................................................................................................................ 10 3. Field Encoding Summary...................................................................................................................................... 12 4. DQ Packet Timing .................................................................................................................................................. 14 5. COLM Packet to D Packet Mapping ..................................................................................................................... 14 6. ROW-to-ROW Packet Interaction.......................................................................................................................... 16 7. ROW-to-COL Packet Interaction........................................................................................................................... 18 8. COL-to-COL Packet Interaction ............................................................................................................................ 19 9. COL-to-ROW Packet Interaction........................................................................................................................... 20 10. ROW-to-ROW Examples...................................................................................................................................... 21 11. Row and Column Cycle Description .................................................................................................................. 22 12. Precharge Mechanisms....................................................................................................................................... 23 13. Read Transaction - Example............................................................................................................................... 25 14. Write Transaction - Example............................................................................................................................... 26 15. Write/Retire - Examples....................................................................................................................................... 27 16. Interleaved Write - Example ................................................................................................................................ 29 17. Interleaved Read - Example ................................................................................................................................ 30 18. Interleaved RRWW - Example ............................................................................................................................. 31 19. Control Register Transactions ........................................................................................................................... 32 20. Control Register Packets .................................................................................................................................... 33 21. Initialization .......................................................................................................................................................... 34 22. Control Register Summary ................................................................................................................................. 38 23. Power State Management ................................................................................................................................... 47 24. Refresh ................................................................................................................................................................. 52 25. Current and Temperature Control ...................................................................................................................... 54 26. Electrical Conditions ........................................................................................................................................... 55 27. Timing Conditions ............................................................................................................................................... 56 28. Electrical Characteristics .................................................................................................................................... 58 29. Timing Characteristics ........................................................................................................................................ 58 30. RSL Clocking ....................................................................................................................................................... 59 31. RSL - Receive Timing .......................................................................................................................................... 60 32. RSL - Transmit Timing......................................................................................................................................... 61 33. CMOS - Receive Timing....................................................................................................................................... 62 34. CMOS - Transmit Timing ..................................................................................................................................... 64 35. RSL - Domain Crossing Window ........................................................................................................................ 65 36. Timing Parameters .............................................................................................................................................. 66 37. Absolute Maximum Ratings................................................................................................................................ 67 6
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
38. IDD - Supply Current Profile ................................................................................................................................. 67 39. Capacitance and Inductance .............................................................................................................................. 68 40. Interleaved Device Mode ..................................................................................................................................... 70 41. Glossary of Terms ............................................................................................................................................... 74 42. Package Drawing ................................................................................................................................................. 76 43. Recommended Soldering Conditions................................................................................................................ 77
Preliminary Data Sheet E0260E40 (Ver. 4.0)
7
EDR2518ABSE
1. General Description
The figure on page 5 is a block diagram of the EDR2518ABSE. It consists of two major blocks : a "core" block built from banks and sense amps similar to those found in other types of DRAM, and a Direct Rambus interface block which permits an external controller to access this core at up to 2.1 GB/s. Control Registers: The CMD, SCK, SIO0, and SIO1 pins appear in the upper center of the block diagram. They are used to write and read a block of control registers. These registers supply the RDRAM device configuration information to a controller and they select the operating modes of the device. The nine bit REFR value is used for tracking the last refreshed row. Most importantly, the five bits DEVID specifies the device address of the RDRAM device on the Channel. Clocking: The CTM and CTMN pins (Clock-To-Master) generate TCLK (Transmit Clock), the internal clock used to transmit read data. The CFM and CFMN pins (Clock-From-Master) generate RCLK (Receive Clock), the internal clock signal used to receive write data and to receive the ROW and COL pins. DQA, DQB Pins: These 18 pins carry read (Q) and write (D) data across the Channel. They are multiplexed / demultiplexed from / to two 72-bit data paths (running at one-eighth the data frequency) inside the RDRAM device. Banks: The 32 Mbyte core of the RDRAM device is divided into 32 one-Mbyte banks, each organized as 512 rows, with each row containing 128 dualocts (2K bytes), and each dualoct containing 16 bytes. A dualoct is the smallest unit of data that can be addressed. Sense Amps: The RDRAM device contains 34 sense amps. Each sense amp consists of 1,024 bytes of fast storage (512 for DQA and 512 for DQB) and can hold one-half of one row of one bank of the RDRAM device. The sense amp may hold any of the 512 half-rows of an associated bank. However, each sense amp is shared between two adjacent banks of the RDRAM device. This introduces the restriction that adjacent banks may not be simultaneously accessed. RQ Pins: These pins carry control and address information. They are broken into two groups. RQ7..RQ5 are also called ROW2..ROW0, and are used primarily for controlling row accesses. RQ4..RQ0 are also called COL4..COL0, and are used primarily for controlling column accesses. ROW Pins: The principle use of these three pins is to manage the transfer of data between the banks and the sense amps of the RDRAM device. These pins are de-multiplexed into a 24-bit ROWA (row-activate) or ROWR (rowoperation) packet. COL Pins: The principle use of these five pins is to manage the transfer of data between the DQA/DQB pins and the sense amps of the RDRAM device. These pins are de-multiplexed into a 23-bit COLC (column-operation) packet and either a 17-bit COLM (mask) packet or a 17-bit COLX (extended-operation) packet. ACT Command: An ACT (activate) command from an ROWA packet causes one of the 512 rows of the selected bank to be loaded to its associated sense amps (two 512 byte sense amps for DQA and two for DQB). PRER Command: A PRER (precharge) command from an ROWR packet causes the selected bank to release its two associated sense amps, permitting a different row in that bank to be activated, or permitting adjacent banks to be activated.
8
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
RD Command: The RD (read) command causes one of the 128 dualocts of one of the sense amps to be transmitted on the DQA/DQB pins of the Channel. WR Command: The WR (write) command causes a dualoct received from the DQA/DQB data pins of the Channel to be loaded into the write buffer. There is also space in the write buffer for the BC bank address and C column address information. The data in the write buffer is automatically retired (written with optional bytemask) to one of the 128 dualocts of one of the sense amps during a subsequent COP command. A retire can take place during a RD, WR, or NOCOP to another device, or during a WR or NOCOP to the same device. The write buffer will not retire during a RD to the same device. The write buffer reduces the delay needed for the internal DQA/DQB data path turnaround. PREC Precharge: The PREC, RDA and WRA commands are similar to NOCOP, RD and WR, except that a precharge operation is performed at the end of the column operation. These commands provide a second mechanism for performing precharge. PREX Precharge: After a RD command, or after a WR command with no byte masking (M=0), a COLX packet may be used to specify an extended operation (XOP). The most important XOP command is PREX. This command provides a third mechanism for performing precharge.
Preliminary Data Sheet E0260E40 (Ver. 4.0)
9
EDR2518ABSE
2. Packet Format
Figure 2-1 shows the formats of the ROWA and ROWR packets on the ROW pins. Table 2-1 describes the fields which comprise these packets. DR4T and DR4F bits are encoded to contain both the DR4 device address bit and a framing bit which allows the ROWA or ROWR packet to be recognized by the RDRAM device. The AV (ROWA/ROWR packet selection) bit distinguishes between the two packet types. Both the ROWA and ROWR packet provide a five bit device address and a four bit bank address. An ROWA packet uses the remaining bits to specify a nine bit row address, and the ROWR packet uses the remaining bits for an eleven bit opcode field. Note the use of the "RsvX" notation to reserve bits for future address field extension. Figure 2-1 also shows the formats of the COLC, COLM, and COLX packets on the COL pins. Table 2-2 describes the fields which comprise these packets. The COLC packet uses the S (Start) bit for framing. A COLM or COLX packet is aligned with this COLC packet, and is also framed by the S bit. The 23 bit COLC packet has a five bit device address, a four bit bank address, a six bit column address, and a four bit opcode. The COLC packet specifies a read or write command, as well as some power management commands. The remaining 17 bits are interpreted as a COLM (M=1) or COLX (M=0) packet. A COLM packet is used for a COLC write command which needs bytemask control. The COLM packet is associated with the COLC packet from a time tRTR earlier. An COLX packet may be used to specify an independent precharge command. It contains a five bit device address, a four bit bank address, and a five bit opcode. The COLX packet may also be used to specify some housekeeping and power management commands. The COLX packet is framed within a COLC packet but is not otherwise associated with any other packet. Table 2-1 Field Description for ROWA Packet and ROWR Packet
Field DR4T, DR4F DR3..DR0 BR4..BR0 AV R8..R0 ROP10..ROP0 Description Bits for framing (recognizing) a ROWA or ROWR packet. Also encodes highest device address bit. Device address for ROWA or ROWR packet. Bank address for ROWA or ROWR packet. RsvB denotes bits ignored by the RDRAM device. Selects between ROWA packet (AV=1) and ROWR packet (AV=0). Row address for ROWA packet. RsvR denotes bits reserved for future row address extension. Opcode field for ROWR packet. Specifies precharge, refresh, and power management functions.
Table 2-2 Field Description for COLC Packet, COLM Packet, and COLX Packet
Field S DC4..DC0 BC4..BC0 C6..C0 COP3..COP0 M MA7..MA0 MB7..MB0 DX4..DX0 BX4..BX0 XOP4..XOP0 Description Bit for framing (recognizing) a COLC packet, and indirectly for framing COLM and COLX packets. Device address for COLC packet. Bank address for COLC packet. RsvB denotes bits reserved for future extension (controller drivers 0's). Column address for COLC packet. Opcode field for COLC packet. Specifies read, write, precharge, and power management functions. Selects between COLM packet (M=1) and COLX packet (M=0). Bytemask write control bits. 1=write, 0=no-write. MA0 controls the earliest byte on DQA8..0. Bytemask write control bits. 1=write, 0=no-write. MB0 controls the earliest byte on DQB8..0. Device address for COLX packet. Bank address for COLX packet. RsvB denotes bits reserved for future extension (controller drivers 0's). Opcode field for COLX packet. Specifies precharge, IOL control, and power management functions.
10
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
Figure 2-1 Packet Formats
T0 T1 T2 T3 T8 T9 T 10 T 11
CTM/CFM
CTM/CFM
ROW2 ROW1 ROW0
DR4T DR2 BR0 BR3 RsvR R8 DR4F DR1 BR1 BR4 RsvR R7 DR3 DR0 BR2 RsvB AV=1 R6
R5 R4 R3
R2 R1 R0
ROW2 ROW1 ROW0
DR4T DR2 BR0 BR3 ROP10ROP8ROP5 ROP2 DR4F DR1 BR1 BR4 ROP9ROP7ROP4ROP1 DR3 DR0 BR2 RsvB AV=0 ROP6ROP3ROP0
ROWA Packet
T0 T1 T2 T3
ROWR Packet
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12 T 13 T 14 T 15
CTM/CFM
DC4 DC3 DC2 COP1 DC1 COP0 DC0 COP2 S=1 C6 C5 RsvB BC2 BC4 BC1 COP3 BC3 BC0 C4 C3 C2 C1 C0
CTM/CFM ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0
ACT a0 PRER c0
COL4 COL3 COL2 COL1 COL0
t PACKET
WR b1 MSK (b1) PREX d0
COLC Packet
T8 T9 T 10 T 11 T 12 T 13 T 14 T 15
CTM/CFM
Note1
CTM/CFM
Note2
COL4 COL3 COL2 COL1 COL0
S=1 MA7 MA5 MA3 MA1 M=1 MA6 MA4 MA2 MA0 MB7 MB4 MB1 MB6 MB3 MB0 MB5 MB2
COL4 COL3 COL2 COL1 COL0
S=1 DX4 XOP4 RsvB BX1 M=0 DX3 XOP3 BX4 BX0 DX2 XOP2 BX3 DX1 XOP1 BX2 DX0 XOP0
COLM Packet
COLX Packet
Notes 1. The COLM is associated with a previous COLC, and is aligned with the present COLC, indicated by the Start bit (S=1) position. 2. The COLX is aligned with the present COLC, indicates by the Start bit (S=1) position.
Preliminary Data Sheet E0260E40 (Ver. 4.0)
11
EDR2518ABSE
3. Field Encoding Summary
Table 3-1 shows how the six device address bits are decoded for the ROWA and ROWR packets. The DR4T and DR4F encoding merges a fifth device bit with a framing bit. When neither bit is asserted, the device is not selected. Note that a broadcast operation is indicated when both bits are set. Broadcast operation would typically be used for refresh and power management commands. If the device is selected, the DM (DeviceMatch) signal is asserted and an ACT or ROP command is performed. Table 3-1 Device Field Encodings for ROWA Packet and ROWR Packet
DR4T 1 0 1 0 DR4F 1 1 0 0 Device Selection All devices (broadcast) One device selected One device selected No packet present Device Match signal (DM) DM is set to 1 DM is set to 1 if {DEVID4..DEVID0} == {0, DR3..DR0} else DM is set to 0 DM is set to 1 if {DEVID4..DEVID0} == {1, DR3..DR0} else DM is set to 0 DM is set to 0
Table 3-2 shows the encodings of the remaining fields of the ROWA and ROWR packets. An ROWA packet is specified by asserting the AV bit. This causes the specified row of the specified bank of this device to be loaded into the associated sense amps. An ROWR packet is specified when AV is not asserted. An 11 bit opcode field encodes a command for one of the banks of this device. The PRER command causes a bank and its two associated sense amps to precharge, so another row or an adjacent bank may be activated. The REFA (refresh-activate) command is similar to the ACT command, except the row address comes from an internal register REFR, and REFR is incremented at the largest bank address. The REFP (refresh-precharge) command is identical to a PRER command. The NAPR, NAPRC, PDNR, ATTN, and RLXR commands are used for managing the power dissipation of the RDRAM and are described in more detail in "23. Power State Management". The TCEN and TCAL commands are used to adjust the output driver slew rate and they are described in more detail in "25. Current and Temperature Control". Table 3-2 ROWA Packet and ROWR Packet Field Encodings
DM
Note1
AV 10 9 -- 1 0 0 0 0 0 0 0 0 0 0 0
ROP10..ROP0 Field 8 7 6 5 -- 4 3 2 :0 ------------ Row address 1 0 1 x x x x x 0 0 0 1 0 0 x x x x x 0 0 0 0 0 1 0 0 0 x x 0 0 0 0 1 0 0 0 0 x x 0 0 0 0 1 1 0 0 0 x x 0 0 0 x
Note3
Name -- ACT
Command Description No operation. Activate row R8..R0 of bank BR4..BR0 of device and move device to ATTN Note2. Precharge bank BR4..BR0 of this device. Refresh (activate) row REFR8..REFR0 of bank BR3..BR0 of device. Increment REFR if BR4..BR0=11111 (see Figure 24-1). Precharge bank BR4..BR0 of this device after REFA (see Figure 24-1). Move this device into the powerdown (PDN) power state (see figure 23-3). Move this device into the nap (NAP) power state (see Figure 23-3). Move this device into the nap (NAP) power state conditionally. Move this device into the attention (ATTN) power state (see Figure 23-1). Move this device into the standby (STBY) power state (see Figure 23-2). Temperature calibrate this device (see figure 25-2). Temperature calibrate/enable this device (see Figure 25-2). No operation.
0 1 1 1 1 1 1 1 1 1 1 1 1
----
x 0 0 1 0 1 x x 0 0 0
x x x x x x 0 1 x x 0
000 PRER 000 REFA 000 REFP 000 PDNR 000 NAPR 000 NAPRC 000 ATTN Note2 000 RLXR 001 TCAL 010 TCEN 000 NOROP
0 0 0 1 1 x x 0 0 0
Notes 1. The DM (Device Match signal) value is determined by the DR4T, DR4F, DR3..DR0 field of the ROWA and ROWR packets. See Table 3-1. 2. The ATTN command does not cause a RLX-to-ATTN transition for a broadcast operation (DR4T/DR4F=1/1). 3. An "x" entry indicates which commands may be combined. For instance, the three commands PRER/NAPRC/RLXR may be specified in one ROP value (011000111000).
12
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
Table 3-3 shows the COP field encoding. The device must be in the ATTN power state in order to receive COLC packets. The COLC packet is used primarily to specify RD (read) and WR (write) commands. Retire operations (moving data from the write buffer to a sense amp) happen automatically. See Figure 15-1 for a more detailed description. The COLC packet can also specify a PREC command, which precharges a bank and its associated sense amps. The RDA/WRA commands are equivalent to a combining RD/WR with a PREC. RLXC (relax) performs a power mode transition. See 23. Power State Management. Table 3-3 COLC Packet Field Encodings
S 0 1 1 1 1 1 1 1 1 1 1 DC4..DC0 (select device) Note1 ---/= (DEVID4..0) == (DEVID4..0) == (DEVID4..0) == (DEVID4..0) == (DEVID4..0) == (DEVID4..0) == (DEVID4..0) == (DEVID4..0) == (DEVID4..0) == (DEVID4..0) COP3..0 --------x000 Note2 x001 x010 x011 x100 x101 x110 x111 1xxx Name -- -- NOCOP WR RSRV RD PREC WRA RSRV RDA RLXC Command Description No operation. Retire write buffer of this device. Retire write buffer of this device. Retire write buffer of this device, then write column C6..C0 of bank BC4..BC0 to write buffer. Reserved, no operation. Read column C6..C0 of bank BC4..BC0 of this device. Retire write buffer of this device, then precharge bank BC4..BC0 (see Figure 12-2). Same as WR, but precharge bank BC4..BC0 after write buffer (with new data) is retired. Reserved, no operation. Same as RD, but precharge bank BC4..BC0 afterward. Move this device into the standby (STBY) power state (see Figure 23-2).
Notes 1. "/=" means not equal, "==" means equal. 2. An "x" entry indicates which commands may be combined. For instance, the two commands WR/RLXC may be specified in one COP value(1001). Table 3-4 shows the COLM and COLX field encodings. The M bit is asserted to specify a COLM packet with two 8 bit bytemask fields MA and MB. If the M bit is not asserted, an COLX is specified. It has device and bank address fields, and an opcode field. The primary use of the COLX packet is to permit an independent PREX (precharge) command to be specified without consuming control bandwidth on the ROW pins. It is also used for the CAL (calibrate) and SAM (sample) current control commands (see 25. Current and Temperature Control), and for the RLXX power mode command (see 23. Power State Management). Table 3-4 COLM Packet and COLX Packet Field Encodings
M 1 0 0 0 0 0 0 0 DX4..DX0 XOP4..0 Name (select device) ---/= (DEVID4..0) == (DEVID4..0) == (DEVID4..0) == (DEVID4..0) == (DEVID4..0) == (DEVID4..0) == (DEVID4..0) 00000 x10x0 x11x0 xxx10 xxxx1 MSK -- NOXOP CAL RLXX RSRV Command Description MB/MA bytemasks used by WR/WRA. No operation. No operation. Precharge bank BX4..BX0 of this device (see Figure 12-2). Calibrate (drive) IOL current for this device (see Figure 25-1). Move this device into the standby (STBY) power state (see Figure 23-2). Reserved, no operation.
1xxx0 Note PREX
CAL / SAM Calibrate (drive) and Sample (update) IOL current for this device (see Figure 25-1).
Note An "x" entry indicates which commands may be combined. For instance, the two commands PREX/RLXX may be specified in one XOP value (10010).
Preliminary Data Sheet E0260E40 (Ver. 4.0)
13
EDR2518ABSE
4. DQ Packet Timing
Figure 4-1 shows the timing relationship of COLC packets with D and Q data packets. This document uses a specific convention for measuring time intervals between packets: all packets on the ROW and COL pins (ROWA, ROWR, COLC, COLM, COLX) use the trailing edge of the packet as a reference point, and all packets on the DQA/DQB pins (D and Q) use the leading edge of the packet as a reference point. An RD or RDA command will transmit a dualoct of read data Q a time tCAC later. This time includes one to five cycles of round-trip propagation delay on the Channel. The tCAC parameter may be programmed to a one of a range of values (8, 9, 10, 11, or 12 tCYCLE). The value chosen depends upon the number of RDRAM devices on the Channel and the RDRAM device timing bin. See Figure 22-1(5/7) "TPARM Register" for more information. A WR or WRA command will receive a dualoct of write data D a time tCWD later. This time does not need to include the round-trip propagation time of the Channel since the COLC and D packets are traveling in the same direction. When a Q packet follows a D packet (shown in the left half of the figure), a gap (tCAC-tCWD) will automatically appear between them because the tCWD value is always less than the tCAC value. There will be no gap between the two COLC packets with the WR and RD commands which schedule the D and Q packets. When a D packet follows a Q packet (shown in the right half of the figure), no gap is needed between them because the tCWD value is less than the tCAC value. However, a gap of tCAC - tCWD or greater must be inserted between the COLC packets with the RD WR commands by the controller so the Q and D packets do not overlap. Figure 4-1 Read (Q) and Write (D) Data Packet - Timing for tCAC = 8,9,10,11 or 12 tCYCLE
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T 20T 21 T 22 T 23 T 24T 25 T 26 T 27T 28T 29 T 30 T 31 T 32T 33 T 34 T 35 T 36T 37 T 38 T 39 T 40T 41 T 42 T 43T 44T 45 T 46 T 47
CTM/CFM
This gap on the DQA/DQB pins appears automatically This gap on the COL pins must be inserted by the controller
ROW2 ..ROW0 t CWD COL4 ..COL0 DQA8..0 DQB8..0
WR a1 RD b1
t CAC -t CWD
***
RD c1 Q (b1) D (a1)
t CAC -t CWD
***
WR d1
t CWD
Q (c1) D (d1)
t CAC
***
***
t CAC
5. COLM Packet to D Packet Mapping
Figure 5-1 shows a write operation initiated by a WR command in a COLC packet. If a subset of the 16 bytes of write data are to be written, then a COLM packet is transmitted on the COL pins a time tRTR after the COLC packet containing the WR command. The M bit of the COLM packet is set to indicate that it contains the MA and MB mask fields. Note that this COLM packet is aligned with the COLC packet which causes the write buffer to be retired. See Figure 15-1 for more details. If all 16 bytes of the D data packet are to be written, then no further control information is required. The packet slot that would have been used by the COLM packet (tRTR after the COLC packet) is available to be used as an COLX packet. This could be used for a PREX precharge command or for a housekeeping command (this case is not shown). The M bit is not asserted in an COLX packet and causes all 16 bytes of the previous WR to be written unconditionally. Note that a RD command will never need a COLM packet, and will always be able to use the COLX packet option (a read operation has no need for the byte-write-enable control bits). The figure 5-1 also shows the mapping between the MA and MB fields of the COLM packet and bytes of the D packet on the DQA and DQB pins. Each mask bit controls whether a byte of data is written (=1) or not written (=0). 14
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
Figure 5-1 Mapping between COLM Packet and D Packet for WR Command
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T 20T 21 T 22 T 23 T 24T 25 T 26 T 27T 28T 29 T 30 T 31 T 32T 33 T 34 T 35 T 36T 37 T 38 T 39 T 40T 41 T 42 T 43T 44T 45 T 46 T 47
CTM/CFM ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0
Transaction a: WR a0 = {Da,Ba,Ra}
ACT a0 PRER a2 ACT b0
t RTR
WR a1 retire (a1) MSK (a1)
t CWD
D (a1)
a1 = {Da,Ba,Ca1}
a3 = {Da,Ba}
COLM Packet
T 17 T 18 T 19 T 20 T 19
D Packet
T 20 T 21 T 22
CTM/CFM
CTM/CFM
COL4 COL3 COL2 COL1 COL0
MA7 MA5 MA3 MA1 M=1 MA6 MA4 MA2 MA0 MB7 MB4 MB1 MB6 MB3 MB0 MB5 MB2
DQB8 DQB7
DB8
DB17 DB26 DB35 DB45 DB53 DB62 DB71
DB7
DB16 DB25 DB34 DB44 DB52 DB61 DB70
* * *
DQB1 DQB0
DB1 DB10 DB19 DB28 DB37 DB46 DB55 DB64
DB0
DB9
DB18 DB27 DB36 DB45 DB54 DB63
MB0 Each bit of the MB7..MB0 field controls writing (=1) or no writing (=0) of the indicated DB bits when the M bit of the COLM packet is one. When M=1, the MA and MB fields control writing of individual data bytes. When M=0, all data bytes are written unconditionally.
MB1
MB2
MB3
MB4
MB5
MB6
MB7
DQA8 DQA7
DA8
DA17 DA26 DA35 DA45 DA53 DA62 DA71
DA7
DA16 DA25 DA34 DA44 DA52 DA61 DA70
* * *
DQA1
Each bit of the MA7..MA0 field controls writing (=1) or no writing (=0) of the indicated DA bits when the M bit of the COLM packet is one. DA1 DA10 DA19 DA28 DA37 DA46 DA55 DA64
DQA0
DA0
DA9
DA18 DA27 DA36 DA45 DA54 DA63
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
Preliminary Data Sheet E0260E40 (Ver. 4.0)
15
EDR2518ABSE
6. ROW-to-ROW Packet Interaction
Figure 6-1 shows two packets on the ROW pins separated by an interval tRRDELAY which depends upon the packet contents. No other ROW packets are sent to banks {Ba, Ba+1, Ba-1} between packet "a" and packet "b" unless noted otherwise. Figure 6-1 ROW-to-ROW Packet Interaction - Timing
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T
CTM/CFM t RRDELAY ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0
Transaction a: ROPa Transaction b: ROPb a0 = {Da,Ba,Ra} b0= {Db,Bb,Rb}
ROPa a0 ROPb b0
Table 6-1 summarizes the tRRDELAY values for all possible cases. Cases RR1 through RR4 show two successive ACT commands. In case RR1, there is no restriction since the ACT commands are to different devices. In case RR2, the tRR restriction applies to the same device with non-adjacent banks. Cases RR3 and RR4 are illegal (as shown) since bank Ba needs to be precharged. If a PRER to Ba, Ba+1, or Ba-1 is inserted, tRRDELAY is tRC (tRAS to the PRER command, and tRP to the next ACT). Cases RR5 through RR8 show an ACT command followed by a PRER command. In cases RR5 and RR6, there are no restrictions since the commands are to different devices or to non-adjacent banks of the same device. In cases RR7 and RR8, the tRAS restriction means the activated bank must wait before it can be precharged. Cases RR9 through RR12 show a PRER command followed by an ACT command. In cases RR9 and RR10, there are essentially no restrictions since the commands are to different devices or to non-adjacent banks of the same device. RR10a and RR10b depend upon whether a bracketed bank (Ba+-1) is precharged or activated. In cases RR11 and RR12, the same and adjacent banks must all wait tRP for the sense amp and bank to precharge before being activated. Cases RR13 through RR16 summarize the combinations of two successive PRER commands. In case RR13 there is no restriction since two devices are addressed. In RR14, tPP applies, since the same device is addressed. In RR15 and RR16, the same bank or an adjacent bank may be given repeated PRER commands with only the tPP restriction. Two adjacent banks can't be activate simultaneously. A precharge command to one bank will thus affect the state of the adjacent banks (and sense amps). If bank Ba is activate and a PRER is directed to Ba, then bank Ba will be precharged along with sense amps Ba-1/Ba and Ba/Ba+1. If bank Ba+1 is activate and a PRER is directed to Ba, then bank Ba+1 will be precharged along with sense amps Ba/Ba+1 and Ba+1/Ba+2. If bank Ba-1 is activate and a PRER is directed to Ba, then bank Ba-1 will be precharged along with sense amps Ba/Ba-1 and Ba-1/Ba-2. A ROW packet may contain commands other than ACT or PRER. The REFA and REFP commands are equivalent to ACT and PRER for interaction analysis purposes. The interaction rules of the NAPR, NAPRC, PDNR, RLXR, ATTN, TCAL, and TCEN commands are discussed in later section (see Table 3-2 for cross-ref).
16
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
Table 6-1 ROW-to-ROW Packet Interaction - Rules
Case # RR1 RR2 RR3 RR4 RR5 RR6 RR7 RR8 RR9 RR10 RR10a RR10b RR11 RR12 RR13 RR14 RR15 RR16 ROPa Da ACT ACT ACT ACT ACT ACT ACT ACT Da Da Da Da Da Da Da Da Ba Ba Ba Ba Ba Ba Ba Ba Ba Ba Ba Ba Ba Ba Ba Ba Ba Ba Ba Ra Ra Ra Ra Ra Ra Ra Ra Ra Ra Ra Ra Ra Ra Ra Ra Ra Ra Ra ROPb Db ACT ACT ACT ACT /= Da Bb xxxx Rb x..x x..x x..x x..x x..x x..x x..x x..x x..x x..x x..x x..x x..x x..x x..x x..x x..x x..x tRRDELAY tPACKET tRR tRC - illegal unless PRER to Ba / Ba+1 / Ba-1 tRC - illegal unless PRER to Ba / Ba+1 / Ba-1 tPACKET tPACKET tRAS tRAS tPACKET tPACKET tPACKET/tRP if Ba+1 is precharged/activated. tPACKET/tRP if Ba-1 is precharged/activated. tRP tRP tPACKET tPP tPP tPP Figure 10-1 Figure 10-1 Figure 10-3 Figure 10-3 Figure 10-3 Figure 10-3 Example Figure 10-2 Figure 10-2 Figure 10-1 Figure 10-1 Figure 10-2 Figure 10-2 Figure 10-1 Figure 13-1 Figure 10-3 Figure 10-3
== Da /= {Ba, Ba+1, Ba-1} == Da == {Ba+1, Ba-1} == Da == {Ba} xxxx
PRER /= Da
PRER == Da /= {Ba, Ba+1, Ba-1} PRER == Da == {Ba+1, Ba-1} PRER == Da == {Ba} ACT ACT ACT ACT ACT ACT /= Da xxxx == Da /= {Ba, Ba+-1, Ba+-2} == Da == {Ba+2} == Da == {Ba-2} == Da == {Ba+1, Ba-1} == Da == {Ba} xxxx
PRER Da PRER Da PRER Da PRER Da PRER Da PRER Da PRER Da PRER Da PRER Da PRER Da
PRER /= Da
PRER == Da /= {Ba, Ba+1, Ba-1} PRER == Da == {Ba+1, Ba-1} PRER == Da == {Ba}
Preliminary Data Sheet E0260E40 (Ver. 4.0)
17
EDR2518ABSE
7. ROW-to-COL Packet Interaction
Figure 7-1 shows two packets on the ROW and COL pins. They must be separated by an interval tRCDELAY which depends upon the packet contents. Figure 7-1 ROW-to-COL Packet Interaction- Timing
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T
CTM/CFM t RCDELAY ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0
Transaction a: ROPa Transaction b: COPb a0 = {Da,Ba,Ra} b1= {Db,Bb,Cb1}
ROPa a0
COPb b1
Table 7-1 summarizes the tRCDELAY values for all possible cases. Note that if the COL packet is earlier than the ROW packet, it is considered a COL-to-ROW packet interaction. Cases RC1 through RC5 summarize the rules when the ROW packet has an ACT command. Figure 13-1 and Figure 14-1 show examples of RC5 - an activation followed by a read or write. RC4 is an illegal situation, since a read or write of a precharged banks is being attempted (remember that for a bank to be activated, adjacent banks must be precharged). In cases RC1, RC2, and RC3, there is no interaction of the ROW and COL packets. Cases RC6 through RC8 summarize the rules when the ROW packet has a PRER command. There is either no interaction (RC6 through RC9) or an illegal situation with a read or write of a precharged bank (RC9). The COL pins can also schedule a precharge operation with a RDA, WRA, or PREC command in a COLC packet or a PREX command in a COLX packet. The constraints of these precharge operations may be converted to equivalent PRER command constraints using the rules summarized in Figure 12-2. Table 7-1 ROW-to-COL Packet Interaction - Rules
Case # ROPa Da RC1 RC2 RC3 RC4 RC5 RC6 RC7 RC8 RC9 ACT ACT ACT ACT ACT Da Da Da Da Da Ba Ba Ba Ba Ba Ba Ba Ba Ba Ba Ra Ra Ra Ra Ra Ra Ra Ra Ra Ra COPb NOCOP RD, retire RD, retire RD, retire NOCOP RD, retire RD, retire Db == Da == Da == Da == Da == Da == Da == Da Bb xxxx xxxx /= {Ba, Ba+1, Ba-1} == {Ba+1, Ba-1} == {Ba} xxxx xxxx /= {Ba, Ba+1, Ba-1} == {Ba+1, Ba-1} Cb1 x..x x..x x..x x..x x..x x..x x..x x..x x..x tRCDELAY Example 0 0 0 Illegal tRCD 0 0 0 Illegal Figure 13-1
NOCOP, RD, retire /= Da
PRER Da PRER Da PRER Da PRER Da
NOCOP, RD, retire /= Da
18
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
8. COL-to-COL Packet Interaction
Figure 8-1 shows three arbitrary packets on the COL pins. Packets "b" and "c" must be separated by an interval tCCDELAY which depends upon the command and address values in all three packets. Table 8-1 summarizes the tCCDELAY values for all possible cases. Cases CC1 through CC5 summarize the rules for every situation other than the case when COPb is a WR command and COPc is a RD command. In CC3, when a RD command is followed by a WR command, a gap of tCAC - tCWD must be inserted between the two COL packets. See Figure 4-1 for more explanation of why this gap is needed. For cases CC1, CC2, CC4, and CC5, there is no restriction (tCCDELAY is tCC). In cases CC6 through CC10, COPb is a WR command and COPc is a RD command. The tCCDELAY value needed between these two packets depends upon the command and address in the packet with COPa. In particular, in case CC6 when there is WR-WR-RD command sequence directed to the same device, a gap will be needed between the packets with COPb and COPc. The gap will need a COLC packet with a NOCOP command directed to any device in order to force an automatic retire to take place. Figure 15-2 (right) provides a more detailed explanation of this case. Cases CC7, CC8, CC9 and CC10 have no restriction (tCCDELAY is tCC). For the purposes of analyzing COL-to-ROW interactions, the PREC, WRA, and RDA commands of the COLC packet are equivalent to the NOCOP, WR, and RD commands. These commands also cause a precharge operation PREC to take place. This precharge may be converted to an equivalent PRER command on the ROW pins using the rules summarized in Figure 12-2. Table 8-1 COL-to-COL Packet Interaction - Rules
Case # CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 CC10 COPa xxxx xxxx xxxx xxxx xxxx WR WR WR RD Da xxxxx xxxxx xxxxx xxxxx xxxxx == Db == Db /= Db == Db Ba x..x x..x x..x x..x x..x x x x x x Ca1 COPb x..x x..x x..x x..x x..x x..x x..x x..x x..x x..x Db Bb Bb Bb Bb Bb Bb Bb Bb Bb Bb Bb Cb1 COPc Cb1 xxxx Cb1 WR Cb1 RD Cb1 WR Cb1 RD Cb1 RD Cb1 RD Cb1 RD Cb1 RD Dc xxxxx xxxxx xxxxx xxxxx == Db /= Db == Db == Db == Db Bc x..x x..x x..x x..x x..x x..x x..x x..x x..x x..x Cc1 tCCDELAY x..x x..x x..x x..x x..x x..x x..x x..x x..x x..x tCC tCC tCC + tCAC - tCWD tCC tCC tRTR tCC tCC tCC tCC Figure 4-1 Figure 13-1 Figure 14-1 Figure 15-1 Example
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T
Figure 8-1 COL-to-COL Packet Interaction- Timing
CTM/CFM ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0
Transaction a: COPa Transaction b: COPb Transaction c: COPc a1 = {Da,Ba,Ca1} b1 = {Db,Bb,Cb1} c1 = {Dc,Bc,Cc1}
t CCDELAY
COPa a1 COPb b1 COPc c1
NOCOP Db RD, WR Db RD RD WR WR WR WR WR WR Db Db Db Db Db Db Db Db
Cb1 NOCOP xxxxx
NOCOP == Db
Preliminary Data Sheet E0260E40 (Ver. 4.0)
19
EDR2518ABSE
9. COL-to-ROW Packet Interaction
Figure 9-1 shows arbitrary packets on the COL and ROW pins. They must be separated by an interval tCRDELAY which depends upon the command and address values in the packets. Table 9-1 summarizes the tCRDELAY value for all possible cases. Cases CR1, CR2, CR3, and CR9 show no interaction between the COL and ROW packets, either because one of the commands is a NOP or because the packets are directed to different devices or to non-adjacent banks. Case CR4 is illegal because an already-activated bank is to be re-activated without being precharged. Case CR5 is illegal because an adjacent bank can't be activated or precharged until bank Ba is precharged first. In case CR6, the COLC packet contains a RD command, and the ROW packet contains a PRER command for the same bank. The tRDP parameter specifies the required spacing. Likewise, in case CR7, the COLC packet causes an automatic retire to take place, and the ROW packet contains a PRER command for the same bank. The tRTP parameter specifies the required spacing. Case CR8 is labeled "Hazardous" because a WR command should always be followed by an automatic retire before a precharge is scheduled. Figure 15-3 shows an example of what can happen when the retire is not able to happen before the precharge. For the purposes of analyzing COL-to-ROW interactions, the PREC, WRA, and RDA commands of the COLC packet are equivalent to the NOCOP, WR, and RD commands. These commands also cause a precharge operation to take place. This precharge may converted to an equivalent PRER command on the ROW pins using the rules summarized in Figure 12-2. A ROW packet may contain commands other than ACT or PRER. The REFA and REFP commands are equivalent to ACT and PRER for interaction analysis purposes. The interaction rules of the NAPR, PDNR, and RLXR commands are discussed in a later section. Table 9-1 COL-to-ROW Packet Interaction - Rules
Case # CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9 COPa NOCOP RD/WR RD/WR RD/WR RD/WR RD retire Note 1 WR Note 2 xxxx Da Da Da Da Da Da Da Da Da Da Ba Ba Ba Ba Ba Ba Ba Ba Ba Ba Ca1 Ca1 Ca1 Ca1 Ca1 Ca1 Ca1 Ca1 Ca1 Ca1 ROPb x..x x..x x..x ACT ACT PRER PRER PRER Db xxxxx /= Da == Da == Da == Da == Da == Da == Da Bb xxxxx xxxxx == {Ba} == {Ba+1, Ba-1} Rb x..x x..x x..x x..x tCRDELAY Example 0 0 0 Illegal Illegal tRDP tRTP 0 0 Figure 13-1 Figure 14-1 Figure 15-3
Transaction a: COPa Transaction b: ROPb a1= {Da,Ba,Ca1} b0= {Db,Bb,Rb}
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T
Figure 9-1 COL-to-ROW Packet Interaction- Timing
CTM/CFM t CRDELAY ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0
COPa a1 ROPb b0
/= {Ba, Ba+1, Ba-1} x..x
== {Ba, Ba+1, Ba-1} x..x == {Ba, Ba+1, Ba-1} x..x == {Ba, Ba+1, Ba-1} x..x xxxxx x..x
NOROP xxxxx
Notes 1. This is any command which permits the write buffer of device Da to retire (see Table 3-3). "Ba" is the bank address in the write buffer. 2. This situation is hazardous because the write buffer will be left unretired while the targeted bank is precharged. See Figure 15-3.
20
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
10. ROW-to-ROW Examples
Figure 10-1 shows examples of some of the ROW-to-ROW packet spacings from Table 6-1. A complete sequence of activate and precharge commands is directed to a bank. The RR8 and RR12 rules apply to this sequence. In addition to satisfying the tRAS and tRP timing parameters, the separation between ACT commands to the same bank must also satisfy the tRC timing parameter (RR4). When a bank is activated, it is necessary for adjacent banks to remain precharged. As a result, the adjacent banks will also satisfy parallel timing constraints; in the example, the RR11 and RR3 rules are analogous to the RR12 and RR4 rules. Figure 10-1 Row Packet Example
Same Device Same Device Same Device Same Device Same Device Adjacent Bank Adjacent Bank Same Bank Adjacent Bank Same Bank RR7 RR3 RR4 RR11 RR12 a0 = {Da,Ba,Ra} a1 = {Da,Ba+1} b0 = {Da,Ba+1,Rb} b0 = {Da,Ba,Rb} b0 = {Da,Ba+1,Rb} b0 = {Da,Ba,Rb}
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T 20T 21 T 22 T 23 T 24T 25 T 26 T 27T 28T 29 T 30 T 31 T 32T 33 T 34 T 35 T 36T 37 T 38 T 39 T 40T 41 T 42 T 43T 44T 45 T 46 T 47
CTM/CFM ROW2 ..ROW0 COL4 ..COL0 t RAS DQA8..0 DQB8..0 t RC
Figure 10-2 shows examples of the ACT-to-ACT (RR1, RR2) and ACT-to-PRER (RR5, RR6) command spacings from Table 6-1. In general, the commands in ROW packets may be spaced an interval tPACKET apart unless they are directed to the same or adjacent banks or unless they are a similar command type (both PRER or both ACT) directed to the same device. Figure 10-2 Row Packet Example
Different Device Same Device Different Device Same Device Any Bank Non-adjacent Bank Any Bank Non-adjacent Bank RR1 RR2 RR5 RR6 a0 = {Da,Ba,Ra} b0 = {Db,Bb,Rb} c0 = {Da,Bc,Rc} b0 = {Db,Bb,Rb} c0 = {Da,Bc,Rc}
ACT a0 PRER a1 ACT b0
t RP
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T 20T 21 T 22 T 23 T 24T 25 T 26 T 27T 28T 29 T 30 T 31 T 32T 33 T 34 T 35 T 36T 37 T 38 T 39 T 40T 41 T 42 T 43T 44T 45 T 46 T 47
CTM/CFM ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0
ACT a0 ACT b0 ACT a0 ACT c0 ACT a0 PRER b0 ACT a0 PRER c0
t PACKET
t RR
t PACKET
t PACKET
Preliminary Data Sheet E0260E40 (Ver. 4.0)
21
EDR2518ABSE
Figure 10-3 shows examples of the PRER-to-PRER (RR13, RR14) and PRER-to-ACT (RR9, RR10) command spacings from Table 6-1. The RR15 and RR16 cases (PRER-to-PRER to same or adjacent banks) are not shown, but are similar to RR14. In general, the commands in ROW packets may be spaced an interval tPACKET apart unless they are directed to the same or adjacent banks or unless they are a similar command type (both PRER or both ACT) directed to the same device. Figure 10-3 Row Packet Example
Different Device Same Device Same Device Same Device Different Device Same Device Any Bank Non-adjacent Bank Ajacent Bank Same Bank Any Bank Non-adjacent Bank RR13 RR14 RR15 RR16 RR9 RR10 a0 = {Da,Ba,Ra} b0 = {Db,Bb,Rb} c0 = {Da,Bc,Rc} c0 = {Da,Ba,Rc} c0 = {Da,Ba+1Rc} b0 = {Db,Bb,Rb} c0 = {Da,Bc,Rc}
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T 20T 21 T 22 T 23 T 24T 25 T 26 T 27T 28T 29 T 30 T 31 T 32T 33 T 34 T 35 T 36T 37 T 38 T 39 T 40T 41 T 42 T 43T 44T 45 T 46 T 47
CTM/CFM ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0
PRER a0 PRER b0 PRER a0 PRER c0 PRER a0 ACT b0 PRER a0 ACT c0
t PACKET
t PP
t PACKET
t PACKET
11. Row and Column Cycle Description
Activate: A row cycle begins with the activate (ACT) operation. The activation process is destructive; the act of sensing the value of a bit in a bank's storage cell transfers the bit to the sense amp, but leaves the original bit in the storage cell with an incorrect value. Restore: Because the activation process is destructive, a hidden operation called restore is automatically performed. The restore operation rewrites the bits in the sense amp back into the storage cells of the activated row of the bank. Read/Write: While the restore operation takes place, the sense amp may be read (RD) and written (WR) using column operations. If new data is written into the sense amp, it is automatically forwarded to the storage cells of the bank so the data in the activated row and the data in the sense amp remain identical. Precharge: When both the restore operation and the column operations are completed, the sense amp and bank are precharged (PRE). This leaves them in the proper state to begin another activate operation. Intervals: The activate operation requires the interval tRCD,MIN to complete. The hidden restore operation requires the interval tRAS,MIN - tRCD,MIN to complete. Column read and write operations are also performed during the tRAS,MIN tRCD,MIN interval (if more than about four column operations are performed, this interval must be increased). The precharge operation requires the interval tRP,MIN to complete. Adjacent Banks: An RDRAM device with a "s" designation (512K x 18 x 32s) indicates it contains "split banks". This means the sense amps are shared between two adjacent banks. When a row in a bank is activated, the two adjacent sense amps are connected to (associated with) that bank and are not available for use by the two adjacent banks. These two adjacent banks must remain precharged while the selected bank goes through its activate, restore, read/write, and precharge operations. For example (referring to the block diagram), if bank 5 is accessed, sense amp 4/5 and sense amp 5/6 will both be loaded with one of the 512 rows (with 1,024 bytes loaded into each sense amp from the 2K byte row - 512 bytes to the DQA side and 512 bytes to the DQB side). While this row from bank 5 is being accessed, no rows may be accessed in banks 4 or 6 because of the sense amp sharing.
22
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
12. Precharge Mechanisms
Figure 12-1 shows an example of precharge with the ROWR packet mechanism. The PRER command must occur a time tRAS after the ACT command, and a time tRP before the next ACT command. This timing will serve as a baseline against which the other precharge mechanisms can be compared. Figure 12-1 Precharge via PRER Command in ROWR Packet
a0 = {Da,Ba,Ra} a5 = {Da,Ba} b0 = {Da,Ba,Rb}
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T 20T 21 T 22 T 23 T 24T 25 T 26 T 27T 28T 29 T 30 T 31 T 32T 33 T 34 T 35 T 36T 37 T 38 T 39 T 40T 41 T 42 T 43T 44T 45 T 46 T 47
CTM/CFM ROW2 ..ROW0 COL4 ..COL0 t RAS DQA8..0 DQB8..0 t RC t RP
ACT a0 PRER a5 ACT b0
Figure 12-2 (top) shows an example of precharge with a RDA command. A bank is activated with an ROWA packet on the ROW pins. Then, a series of four dualocts are read with RD commands in COLC packets on the COL pins. The fourth of these commands is a RDA, which causes the bank to automatically precharge when the final read has finished. The timing of this automatic precharge is equivalent to a PRER command in an ROWR packet on the ROW pins that is offset a time tOFFP from the COLC packet with the RDA command. The RDA command should be treated as a RD command in a COLC packet as well as a simultaneous (but offset) PRER command in an ROWR packet when analyzing interactions with other packets. Figure 12-2 (middle) shows an example of precharge with a WRA command. As in the RDA example, a bank is activated with an ROWA packet on the ROW pins. Then, two dualocts are written with WR commands in COLC packets on the COL pins. The second of these commands is a WRA, which causes the bank to automatically precharge when the final write has been retired. The timing of this automatic precharge is equivalent to a PRER command in an ROWR packet on the ROW pins that is offset a time tOFFP from the COLC packet that causes the automatic retire. The WRA command should be treated as a WR command in a COLC packet as well as a simultaneous (but offset) PRER command in an ROWR packet when analyzing interactions with other packets. Note that the automatic retire is triggered by a COLC packet a time tRTR after the COLC packet with the WR command unless the second COLC contains a RD command to the same device. This is described in more detail in Figure 151. Figure 12-2 (bottom) shows an example of precharge with a PREX command in an COLX packet. A bank is activated with an ROWA packet on the ROW pins. Then, a series of four dualocts are read with RD commands in COLC packets on the COL pins. The fourth of these COLC packets includes an COLX packet with a PREX command. This causes the bank to precharge with timing equivalent to a PRER command in an ROWR packet on the ROW pins that is offset a time tOFFP from the COLX packet with the PREX command.
Preliminary Data Sheet E0260E40 (Ver. 4.0)
23
EDR2518ABSE
Figure 12-2 Offsets for Alternate Precharge Mechanisms
COLC Packet: RDA Precharge Offset
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T 20T 21 T 22 T 23 T 24T 25 T 26 T 27T 28T 29 T 30 T 31 T 32T 33 T 34 T 35 T 36T 37 T 38 T 39 T 40T 41 T 42 T 43T 44T 45 T 46 T 47
CTM/CFM
The RDA precharge is equivalent to a PRER command here
ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0
ACT a0
PRER a5
ACT b0
t OFFP
RD a1 RD a2 RD a3 RDA a4
Q (a1)
Q (a2)
Q (a3)
Q (a4)
Transaction a: RD
a0 = {Da,Ba,Ra}
a1 = {Da,Ba,Ca1} a3 = {Da,Ba,Ca3}
a2 = {Da,Ba,Ca2} a4 = {Da,Ba,Ca4}
a5 = {Da,Ba}
COLC Packet: WDA Precharge Offset
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T 20T 21 T 22 T 23 T 24T 25 T 26 T 27T 28T 29 T 30 T 31 T 32T 33 T 34 T 35 T 36T 37 T 38 T 39 T 40T 41 T 42 T 43T 44T 45 T 46 T 47
CTM/CFM
The WRA precharge (triggered by the automatic retire) is equivalent to a PRER command here
ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0
ACT a0
PRER a5
ACT b0
t RTR
WR a1 WRA a2 retire (a1) retire (a2) MSK (a1) MSK (a2)
t OFFP
D (a1)
D (a2)
Transaction a: WR
a0 = {Da,Ba,Ra}
a1 = {Da,Ba,Ca1}
a2 = {Da,Ba,Ca2}
a5 = {Da,Ba}
COLX Packet: PREX Precharge Offset
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T 20T 21 T 22 T 23 T 24T 25 T 26 T 27T 28T 29 T 30 T 31 T 32T 33 T 34 T 35 T 36T 37 T 38 T 39 T 40T 41 T 42 T 43T 44T 45 T 46 T 47
CTM/CFM
The PREX precharge command is equivalent to a PRER command here
ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0
ACT a0
PRER a5
ACT b0
t OFFP
RD a1 RD a2 RD a3 RD a4 PREX a5
Q (a1)
Q (a2)
Q (a3)
Q (a4)
Transaction a: RD
a0 = {Da,Ba,Ra}
a1 = {Da,Ba,Ca1} a3 = {Da,Ba,Ca3}
a2 = {Da,Ba,Ca2} a4 = {Da,Ba,Ca4}
a5 = {Da,Ba}
24
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
13. Read Transaction - Example
Figure 13-1 shows an example of a read transaction. It begins by activating a bank with an ACT a0 command in an ROWA packet. A time tRCD later a RD a1 command is issued in a COLC packet. Note that the ACT command includes the device, bank, and row address (abbreviated as a0) while the RD command includes device, bank, and column address (abbreviated as a1). A time tCAC after the RD command the read data dualoct Q (a1) is returned by the device. Note that the packets on the ROW and COL pins use the end of the packet as a timing reference point, while the packets on the DQA/DQB pins use the beginning of the packet as a timing reference point. A time tCC after the first COLC packet on the COL pins a second is issued. It contains a RD a2 command. The a2 address has the same device and bank address as the a1 address (and a0 address), but a different column address. A time tCAC after the second RD command a second read data dualoct Q(a2) is returned by the device. Next, a PRER a3 command is issued in an ROWR packet on the ROW pins. This causes the bank to precharge so that a different row may be activated in a subsequent transaction or so that an adjacent bank may be activated. The a3 address includes the same device and bank address as the a0, a1, and a2 addresses. The PRER command must occur a time tRAS or more after the original ACT command (the activation operation in any DRAM is destructive, and the contents of the selected row must be restored from the two associated sense amps of the bank during the tRAS interval). The PRER command must also occur a time tRDP or more after the last RD command. Note that the tRDP value shown is greater than the tRDP,MIN specification in "36.Timing Parameters". This transaction example reads two dualocts, but there is actually enough time to read three dualocts before tRDP becomes the limiting parameter rather than tRAS. If four dualocts were read, the packet with PRER would need to shift right (be delayed) by one tCYCLE (note-this case is not shown). Finally, an ACT b0 command is issued in an ROWR packet on the ROW pins. The second ACT command must occur a time tRC or more after the first ACT command and a time tRP or more after the PRER command. This ensures that the bank and its associated sense amps are precharged. This example assumes that the second transaction has the same device and bank address as the first transaction, but a different row address. Transaction b may not be started until transaction a has finished. However, transactions to other banks or other devices may be issued during transaction a. Figure 13-1 Read Transaction Example
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T 20T 21 T 22 T 23 T 24T 25 T 26 T 27T 28T 29 T 30 T 31 T 32T 33 T 34 T 35 T 36T 37 T 38 T 39 T 40T 41 T 42 T 43T 44T 45 T 46 T 47
CTM/CFM t RC ROW2 ..ROW0 COL4 ..COL0 t RCD DQA8..0 DQB8..0 t CAC
Transaction a: RD Transaction b: xx a0 = {Da,Ba,Ra} b0 = {Da,Ba,Rb}
ACT a0 PRER a3 ACT b0
t RAS
RD a1 RD a2
t RP t RDP
Q (a1) Q (a2)
t CC
t CAC
a1 = {Da,Ba,Ca1} a2 = {Da,Ba,Ca2} a3 = {Da,Ba}
Preliminary Data Sheet E0260E40 (Ver. 4.0)
25
EDR2518ABSE
14. Write Transaction - Example
Figure 14-1 shows an example of a write transaction. It begins by activating a bank with an ACT a0 command in an ROWA packet. A time tRCD - tRTR later a WR a1 command is issued in a COLC packet (note that the tRCD interval is measured to the end of the COLC packet with the first retire command). Note that the ACT command includes the device, bank, and row address (abbreviated as a0) while the WR command includes device, bank, and column address (abbreviated as a1). A time tCWD after the WR command the write data dualoct D(a1) is issued. Note that the packets on the ROW and COL pins use the end of the packet as a timing reference point, while the packets on the DQA/DQB pins use the beginning of the packet as a timing reference point. A time tCC after the first COLC packet on the COL pins a second COLC packet is issued. It contains a WR a2 command. The a2 address has the same device and bank address as the a1 address (and a0 address), but a different column address. A time tCWD after the second WR command a second write data dualoct D(a2) is issued. A time tRTR after each WR command an optional COLM packet MSK (a1) is issued, and at the same time a COLC packet is issued causing the write buffer to automatically retire. See Figure 15-1 for more detail on the write/retire mechanism. If a COLM packet is not used, all data bytes are unconditionally written. If the COLC packet which causes the write buffer to retire is delayed, then the COLM packet (if used) must also be delayed. Next, a PRER a3 command is issued in an ROWR packet on the ROW pins. This causes the bank to precharge so that a different row may be activated in a subsequent transaction or so that an adjacent bank may be activated. The a3 address includes the same device and bank address as the a0, a1, and a2 addresses. The PRER command must occur a time tRAS or more after the original ACT command (the activation operation in any DRAM is destructive, and the contents of the selected row must be restored from the two associated sense amps of the bank during the tRAS interval). A PRER a3 command is issued in an ROWR packet on the ROW pins. The PRER command must occur a time tRTP or more after the last COLC which causes an automatic retire. Finally, an ACT b0 command is issued in an ROWR packet on the ROW pins. The second ACT command must occur a time tRC or more after the first ACT command and a time tRP or more after the PRER command. This ensures that the bank and its associated sense amps are precharged. This example assumes that the second transaction has the same device and bank address as the first transaction, but a different row address. Transaction b may not be started until transaction a has finished. However, transactions to other banks or other devices may be issued during transaction a. Figure 14-1 Write Transaction Example
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T 20T 21 T 22 T 23 T 24T 25 T 26 T 27T 28T 29 T 30 T 31 T 32T 33 T 34 T 35 T 36T 37 T 38 T 39 T 40T 41 T 42 T 43T 44T 45 T 46 T 47
CTM/CFM t RC ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0
ACT a0 PRER a3 ACT b0
t RCD t RAS
WR a1 WR a2 retire (a1) retire (a2) MSK (a1) MSK (a2)
t RP t RTP t RTR
D (a1) D (a2)
t RTR t CC t CWD
Transaction a: WR Transaction b: xx a0 = {Da,Ba,Ra} b0 = {Da,Ba,Rb}
t CWD
a1 = {Da,Ba,Ca1} a2 = {Da,Ba,Ca2} a3 = {Da,Ba}
26
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
15. Write/Retire - Examples
The process of writing a dualoct into a sense amp of an RDRAM bank occurs in two steps. The first step consists of transporting the write command, write address, and write data into the write buffer. The second step happens when the RDRAM device automatically retires the write buffer (with an optional bytemask) into the sense amp. This twostep write process reduces the natural turn-around delay due to the internal bidirectional data pins. Figure 15-1 (left) shows an example of this two step process. The first COLC packet contains the WR command and an address specifying device, bank and column. The write data dualoct follows a time tCWD later. This information is loaded into the write buffer of the specified device. The COLC packet which follows a time tRTR later will retire the write buffer. The retire will happen automatically unless (1) a COLC packet is not framed (no COLC packet is present and the S bit is zero), or (2) the COLC packet contains a RD command to the same device. If the retire does not take place at time tRTR after the original WR command, then the device continues to frame COLC packets, looking for the first that is not a RD directed to itself. A bytemask MSK(a1) may be supplied in a COLM packet aligned with the COLC that retires the write buffer at time tRTR after the WR command. The memory controller must be aware of this two-step write/retire process. Controller performance can be improved, but only if the controller design accounts for several side effects. Figure 15-1 (right) shows the first of these side effects. The first COLC packet has a WR command which loads the address and data into the write buffer. The third COLC causes an automatic retire of the write buffer to the sense amp. The second and fourth COLC packets (which bracket the retire packet) contain RD commands with the same device, bank and column address as the original WR command. In other words, the same dualoct address that is written is read both before and after it is actually retired. The first RD returns the old dualoct value from the sense amp before it is overwritten. The second RD returns the new dualoct value that was just written. Figure 15-1 Normal Retire (left) and Retire/Read Ordering (right)
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T 20T 21 T 22 T23 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T 20T 21 T 22 T 23 0
CTM/CFM ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0 t CWD
Transaction a: WR a1= {Da,Ba,Ca1} Retire is automatic here unless: (1) No COLC packet (S=0) or (2) COLC packet is RD to device Da
CTM/CFM
This RD gets the old data This RD gets the new data
ROW2 ..ROW0 t CAC t CAC COL4 ..COL0 DQA8..0 DQB8..0 t CWD Transaction a: WR Transaction b: RD Transaction c: RD
WR a1 RD b1 retire (a1) MSK (a1) RD c1
WR a1
retire (a1) MSK (a1)
t RTR
D (a1)
t RTR
D (a1) Q (b1) Q(
a1= {Da,Ba,Ca1} b1= {Da,Ba,Ca1} c1= {Da,Ba,Ca1}
Figure 15-2 (left) shows the result of performing a RD command to the same device in the same COLC packet slot that would normally be used for the retire operation. The read may be to any bank and column address; all that matters is that it is to the same device as the WR command. The retire operation and MSK(a1) will be delayed by a time tPACKET as a result. If the RD command used the same bank and column address as the WR command, the old data from the sense amp would be returned. If many RD commands to the same device were issued instead of the single one that is shown, then the retire operation would be held off an arbitrarily long time. However, once a RD to another device or a WR or NOCOP to any device is issued, the retire will take place. Figure 15-2 (right) illustrates a situation in which the controller wants to issue a WR-WR-RD COLC packet sequence, with all commands addressed to the same device, but addressed to any combination of banks and columns. The RD will prevent a retire of the first WR from automatically happening. But the first dualoct D(a1) in the write
Preliminary Data Sheet E0260E40 (Ver. 4.0)
27
EDR2518ABSE
buffer will be overwritten by the second WR dualoct D(b1) if the RD command is issued in the third COLC packet. Therefore, it is required in this situation that the controller issue a NOCOP command in the third COLC packet, delaying the RD command by a time of tPACKET. This situation is explicitly shown in Table 8-1 for the cases in which tCCDELAY is equal to tRTR. Figure 15-2 Retire Held Off by Read (left) and Controller Forces WWR Gap (right)
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T 20T 21 T 22 T 23 T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T 20
CTM/CFM ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0 t CWD Transaction a: WR Transaction b: RD
The retire operation for a write can be held off by a read to the same device
CTM/CFM ROW2 ..ROW0 COL4 ..COL0
Q (b1) DQA8..0
The controller must insert a NOCOP to retire (a1) to make room for the data (b1) in the write buffer
t CAC
WR a1 RD b1 retire (a1) MSK (a1) WR a1 WR b1 retire (a1) MSK (a1) RD c1
t CAC t RTR
D (a1) D (b1)
t RTR + tPACKET
D (a1)
DQB8..0
a1= {Da,Ba,Ca1} b1= {Da,Bb,Cb1}
t CWD Transaction a: WR Transaction b: WR Transaction c: RD
a1= {Da,Ba,Ca1} b1= {Da,Bb,Cb1} c1= {Da,Bc,Cc1}
Figure 15-3 shows a possible result when a retire is held off for a long time (an extended version of Figure 15-2-left). After a WR command, a series of six RD commands are issued to the same device (but to any combination of bank and column addresses). In the meantime, the bank Ba to which the WR command was originally directed is precharged, and a different row Rc is activated. When the retire is automatically performed, it is made to this new row, since the write buffer only contains the bank and column address, not the row address. The controller can insure that this doesn't happen by never precharging a bank with an unretired write buffer. Note that in a system with more than one RDRAM device, there will never be more than two RDRAM devices with unretired write buffers. This is because a WR command issued to one device automatically retires the write buffers of all other devices written a time tRTR before or earlier. Figure 15-3 Retire Held Off by Reads to Same Device, Write Buffer Retired to New Row
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T 20T 21 T 22 T 23 T 24T 25 T 26 T 27T 28T 29 T 30 T 31 T 32T 33 T 34 T 35 T 36T 37 T 38 T 39 T 40T 41 T 42 T 43T 44T 45 T 46 T 47
CTM/CFM t RC ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0
Transaction a: WR Transaction b: RD Transaction c: WR
ACT a0 PRER a2 ACT c0
The retire operation puts the write data in the new row
t RAS
WR a1 RD b1 RD b2 RD b3
t RP
RD b4 RD b5 RD b6 retire (a1) MSK (a1)
t RCD
t RTR
D (a1) Q (b1) Q (b2) Q (b3) Q (b4) Q (b5)
t CWD t CAC a1 = {Da,Ba,Ca1} a2 = {Da,Ba} a0 = {Da,Ba,Ra} b1 = {Da,Bb,Cb1} b2 = {Da,Bb,Cb2} b3= {Da,Bb,Cb3} b5 = {Da,Bb,Cb5} b4 = {Da,Bb,Cb4} b6 = {Da,Bb,Cb6} c0 = {Da,Ba,Rc}
WARNING This sequence is hazardous and must be used with caution
28
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
16. Interleaved Write - Example
Figure 16-1 shows an example of an interleaved write transaction. Transactions similar to the one presented in Figure 14-1 are directed to non-adjacent banks of a single RDRAM device. This allows a new transaction to be issued once every tRR interval rather than once every tRC interval (four times more often). The DQ data pin efficiency is 100% with this sequence. With two dualocts of data written per transaction, the COL, DQA, and DQB pins are fully utilized. Banks are precharged using the WRA autoprecharge option rather than the PRER command in an ROWR packet on the ROW pins. In this example, the first transaction is directed to device Da and bank Ba. The next three transactions are directed to the same device Da, but need to use different, non-adjacent banks Bb, Bc, Bd so there is no bank conflict. The fifth transaction could be redirected back to bank Ba without interference, since the first transaction would have completed by then (tRC has elapsed). Each transaction may use any value of row address (Ra, Rb, ...) and column address (Ca1, Ca2, Cb1, Cb2, ...). Figure 16-1 Interleaved Write Transaction with Two Dualoct Data Length
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T 20T 21 T 22 T 23 T 24T 25 T 26 T 27T 28T 29 T 30 T 31 T 32T 33 T 34 T 35 T 36T 37 T 38 T 39 T 40T 41 T 42 T 43T 44T 45 T 46 T 47
CTM/CFM t RC ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0
ACT a0 ACT b0 ACT c0 ACT d0 ACT e0
Transaction e can use the same bank as transaction a
ACT f0
t RCD
WR z1 WRA z2 MSK (y1) MSK (y2) WR a1 WRA a2 WR b1 WRA b2 WR c1 WRA c2 MSK (z1) MSK (z2) MSK (a1) MSK (a2) MSK (b1) MSK (b2)
t RR
WR d1 WR d2 WR e1 WR e2 MSK (c1) MSK (c2) MSK (d1) MSK (d2)
t CWD
D (x2) D (y1) D (y2) D (z1) D (z2) D (a1) D (a2) D (b1) D (b2) D(c1) D (c2) D (d1) Q(
Transaction y: WR Transaction z: WR Transaction a: WR Transaction b: WR Transaction c: WR Transaction d: WR Transaction e: WR Transaction f: WR
y0 = {Da,Ba+4,Ry} z0 = {Da,Ba+6,Rz} a0 = {Da,Ba,Ra} b0 = {Da,Ba+2,Rb} c0 = {Da,Ba+4,Rc} d0 = {Da,Ba+6,Rd} e0 = {Da,Ba,Re} f0 = {Da,Ba+2,Rf}
y1 = {Da,Ba+4,Cy1} z1 = {Da,Ba+6,Cz1} a1 = {Da,Ba,Ca1} b1 = {Da,Ba+2,Cb1} c1 = {Da,Ba+4,Cc1} d1 = {Da,Ba+6,Cd1} e1 = {Da,Ba,Ce1} f1 = {Da,Ba+2,Cf1}
y2= {Da,Ba+4,Cy2} z2= {Da,Ba+6,Cz2} a2= {Da,Ba,Ca2} b2= {Da,Ba+2,Cb2} c2= {Da,Ba+4,Cc2} d2= {Da,Ba+6,Cd2} e2= {Da,Ba,Ce2} f2= {Da,Ba+2,Cf2}
y3 = {Da,Ba+4} z3 = {Da,Ba+6} a3 = {Da,Ba} b3 = {Da,Ba+2} c3 = {Da,Ba+4} d3 = {Da,Ba+6} e3 = {Da,Ba} f3 = {Da,Ba+2}
Preliminary Data Sheet E0260E40 (Ver. 4.0)
29
EDR2518ABSE
17. Interleaved Read - Example
Figure 17-1 shows an example of interleaved read transactions. Transactions similar to the one presented in Figure 13-1 are directed to non-adjacent banks of a single RDRAM device. The address sequence is identical to the one used in the previous write example. The DQ data pins efficiency is also 100%. The only difference with the write example (aside from the use of the RD command rather than the WR command) is the use of the PREX command in a COLX packet to precharge the banks rather than the RDA command. This is done because the PREX is available for a read transaction but is not available for a masked write transaction. Figure 17-1 Interleaved Read Transaction with Two Dualoct Data Length
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T 20T 21 T 22 T 23 T 24T 25 T 26 T 27T 28T 29 T 30 T 31 T 32T 33 T 34 T 35 T 36T 37 T 38 T 39 T 40T 41 T 42 T 43T 44T 45 T 46 T 47
CTM/CFM t RC ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0
ACT a0 ACT b0 ACT c0 ACT d0 ACT e0
Transaction e can use the same bank as transaction a
ACT f0
t RCD
RD z1 RD z2 PREX y3 RD a1 RD a2 PREX z3 RD b1 RD b2 PREX a3 RD c1
t RR
RD c2 PREX b3 RD d1 RDd2 PREX c3 RD e1 RD e2 PREX d3
t CAC
Q (x2) Q (y1) Q (y2) Q (z1) Q (z2) Q (a1) Q (a2) Q (b1) Q (b2) Q (c1) Q (c2) Q (d1)
Transaction y: RD Transaction z: RD Transaction a: RD Transaction b: RD Transaction c: RD Transaction d: RD Transaction e: RD Transaction f: RD
y0 = {Da,Ba+4,Ry} z0 = {Da,Ba+6,Rz} a0 = {Da,Ba,Ra} b0 = {Da,Ba+2,Rb} c0 = {Da,Ba+4,Rc} d0 = {Da,Ba+6,Rd} e0 = {Da,Ba,Re} f0 = {Da,Ba+2,Rf}
y1 = {Da,Ba+4,Cy1} z1 = {Da,Ba+6,Cz1} a1 = {Da,Ba,Ca1} b1 = {Da,Ba+2,Cb1} c1 = {Da,Ba+4,Cc1} d1 = {Da,Ba+6,Cd1} e1 = {Da,Ba,Ce1} f1 = {Da,Ba+2,Cf1}
y2= {Da,Ba+4,Cy2} z2= {Da,Ba+6,Cz2} a2= {Da,Ba,Ca2} b2= {Da,Ba+2,Cb2} c2= {Da,Ba+4,Cc2} d2= {Da,Ba+6,Cd2} e2= {Da,Ba,Ce2} f2= {Da,Ba+2,Cf2}
y3 = {Da,Ba+4} z3 = {Da,Ba+6} a3 = {Da,Ba} b3 = {Da,Ba+2} c3 = {Da,Ba+4} d3 = {Da,Ba+6} e3 = {Da,Ba} f3 = {Da,Ba+2}
30
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
18. Interleaved RRWW - Example
Figure 18-1 shows a steady-state sequence of 2-dualoct RD/RD/WR/WR.. transactions directed to non-adjacent banks of a single RDRAM device. This is similar to the interleaved write and read examples in Figure 16-1 and Figure 17-1 except that bubble cycles need to be inserted by the controller at read/write boundaries. The DQ data pin efficiency for the example in Figure 18-1 is 32/42 or 76%. If there were more RDRAM devices on the Channel, the DQ pin efficiency would approach 32/34 or 94% for the two-dualoct RRWW sequence (this case is not shown). In Figure 18-1, the first bubble type tCBUB1 is inserted by the controller between a RD and WR command on the COL pins. This bubble accounts for the round-trip propagation delay that is seen by read data, and is explained in detail in Figure 4-1. This bubble appears on the DQA and DQB pins as tDBUB1 between a write data dualoct D and read data dualoct Q. This bubble also appears on the ROW pins as tRBUB1. The second bubble type tCBUB2 is inserted (as a NOCOP command) by the controller between a WR and RD command on the COL pins when there is a WR-WR-RD sequence to the same device. This bubble enables write data to be retired from the write buffer without being lost, and is explained in detail in Figure 15-2. There would be no bubble if address c0 and address d0 were directed to different devices. This bubble appears on the DQA and DQB pins as tDBUB2 between a write data dualoct D and read data dualoct Q. This bubble also appears on the ROW pins as tRBUB2. Figure 18-1 Interleaved RRWW Sequence with Two Dualoct Data Length
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T 20T 21 T 22 T 23 T 24T 25 T 26 T 27T 28T 29 T 30 T 31 T 32T 33 T 34 T 35 T 36T 37 T 38 T 39 T 40T 41 T 42 T 43T 44T 45 T 46 T 47
CTM/CFM t RBUB1 ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0
ACT a0 ACT b0 ACT c0
t RBUB2
Transaction e can use the same bank as transaction a ACT d0 ACT e0
t CBUB2
RD z1 RD z2 RD a1 RD a2 PREX z3
t CBUB1
WR b1 MSK (y2) WRA b2 WR c1 WRA c2 PREX a3 MSK (b1) MSK (b2)
t CBUB2
NOCOP NOCOP MSK (c1) MSK (c2) RDd0 RD f
tDBUB1
D (y2)
t DBUB2
Q (z1) Q (z2) Q (a1) Q (a2) D (b1) D (b2) D (c1)
t DBUB1
D (c2)
Transaction y: WR Transaction z: RD Transaction a: RD Transaction b: WR Transaction c: WR Transaction d: RD Transaction e: RD Transaction f: WR
y0 = {Da,Ba+4,Ry} z0 = {Da,Ba+6,Rz} a0 = {Da,Ba,Ra} b0 = {Da,Ba+2,Rb} c0 = {Da,Ba+4,Rc} d0 = {Da,Ba+6,Rd} e0 = {Da,Ba,Re} f0 = {Da,Ba+2,Rf}
y1 = {Da,Ba+4,Cy1} z1 = {Da,Ba+6,Cz1} a1 = {Da,Ba,Ca1} b1 = {Da,Ba+2,Cb1} c1 = {Da,Ba+4,Cc1} d1 = {Da,Ba+6,Cd1} e1 = {Da,Ba,Ce1} f1 = {Da,Ba+2,Cf1}
y2= {Da,Ba+4,Cy2} z2= {Da,Ba+6,Cz2} a2= {Da,Ba,Ca2} b2= {Da,Ba+2,Cb2} c2= {Da,Ba+4,Cc2} d2= {Da,Ba+6,Cd2} e2= {Da,Ba,Ce2} f2= {Da,Ba+2,Cf2}
y3 = {Da,Ba+4} z3 = {Da,Ba+6} a3 = {Da,Ba} b3 = {Da,Ba+2} c3 = {Da,Ba+4} d3 = {Da,Ba+6} e3 = {Da,Ba} f3 = {Da,Ba+2}
Preliminary Data Sheet E0260E40 (Ver. 4.0)
31
EDR2518ABSE
19. Control Register Transactions
The RDRAM device has two CMOS input pins SCK and CMD and two CMOS input/output pins SIO0 and SIO1. These provide serial access to a set of control registers in the device. These control registers provide configuration information to the controller during the initialization process. They also allow an application to select the appropriate operating mode of the device. SCK (serial clock) and CMD (command) are driven by the controller to all devices in parallel. SIO0 and SIO1 are connected (in a daisy chain fashion) from one device to the next. In normal operation, the data on SIO0 is repeated on SIO1, which connects to SIO0 of the next device (the data is repeated from SIO1 to SIO0 for a read data packet). The controller connects to SIO0 of the first device. Write and read transactions are each composed of four packets, as shown in Figure 19-1 and Figure 19-2. Each packet consists of 16 bits, as summarized in Table 20-1 and Table 20-2. The packet bits are sampled on the falling edge of SCK. A transaction begins with a SRQ (Serial Request) packet. This packet is framed with a 11110000 pattern on the CMD input (note that the CMD bits are sampled on both the falling edge and the rising edge of SCK). The SRQ packet contains the SOP3..SOP0 (Serial Opcode) field, which selects the transaction type. The SDEV5..SDEV0 (Serial Device address) selects one of the 32 devices. If SBC (Serial Broadcast) is set, then all devices are selected. The SA (Serial Address) packet contains a 12 bit address for selecting a control register. A write transaction has a SD (Serial Data) packet next. This contains 16 bits of data that is written into the selected control register. A SINT (Serial Interval) packet is last, providing some delay for any side-effects to take place. A read transaction has a SINT packet, then a SD packet. This provides delay for the selected device to access the control register. The SD read data packet travels in the opposite direction (towards the controller) from the other packet types. Because the device drives data on the falling SCK edge, the read data transmit window is offset tSCYCLE/2 relative to the other packet types. The SCK cycle time will accommodate the total propagation delay. Figure 19-1 Serial Write (SWR) Transaction to Control Register
SCK T4 T 20 T 36 T 52 T 68 1 0 CMD
1111 0000
next transaction
00000000...00000000 00000000...00000000 00000000...00000000 00000000...00000000
1111
1 0 1
SIO0
SRQ - SWR command SA SD SINT
SIO1
Each packet is repeated from SIO0 to SIO1
SRQ - SWR command SA SD SINT
0 1 0
Figure 19-2 Serial Read (SRD) Transaction Control Register
SCK T4 T 20 T 36 T 52 T 68 1 0 CMD
1111 0000
next transaction
1
1111
00000000...00000000
00000000...00000000
00000000...00000000
addressed RDRAM devices 0/SD15..SD0/0 on SIO0
00000000...00000000
controller drives 0 on SIO0
0 1
0
SIO 0
SRQ - SRD command SA
SINT
0
SD
SIO 1
First 3 packets are repeated from SIO0 to SIO1
SRQ - SRD command SA SINT
0
non addressed RDRAMs pass 0/SD15..SD0/0 from SIO1 to SIO0
0 1 0
SD
0
32
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
20. Control Register Packets
Table 20-1 summarizes the formats of the four packet types for control register transactions. Table 20-2 summarizes the fields that are used within the packets. Figure 20-1 shows the transaction format for the SETR, CLRR, and SETF commands. These transactions consist of a single SRQ packet, rather than four packets like the SWR and SRD commands. The same framing sequence on the CMD input is used, however.
SIO0
SRQ packet - SETR/CLRR/SETF The packet is repeated from SIO0 to SIO1
Figure 20-1 SETR, CLRR, SETF Transaction
T4 SCK 0 1 CMD
1111 0000 00000000...00000000
T 20 1
0 1 0 1 0
SIO1
SRQ packet - SETR/CLRR/SETF
Table 20-1 Control Register Packet Formats
SCK Cycle 0 1 2 3 4 5 6 7 SIO0 or SIO1 for SRQ rsrv rsrv rsrv rsrv rsrv SDEV5 SOP3 SOP2 SIO0 or SIO1 for SA rsrv rsrv rsrv rsrv SA11 SA10 SA9 SA8 SIO0 or SIO1 for SINT 0 0 0 0 0 0 0 0 SIO0 or SIO1 for SD SD15 SD14 SD13 SD12 SD11 SD10 SD9 SD8 SCK Cycle 8 9 10 11 12 13 14 15 SIO0 or SIO1 for SRQ SOP1 SOP0 SBC SDEV4 SDEV3 SDEV2 SDEV1 SDEV0 SIO0 or SIO1 for SA SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 SIO0 or SIO1 for SINT 0 0 0 0 0 0 0 0 SIO0 or SIO1 for SD SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
Table 20-2 Field Description for Control Register Packets
Field rsrv SOP3..SOP0 Description Reserved. Should be driven as "0" by controller. 0000 - SRD. Serial read of control register {SA11..SA0} of RDRAM device {SDEV5..SDEV0}. 0001 - SWR. Serial write of control register {SA11..SA0} of RDRAM device {SDEV5..SDEV0}. 0010 - SETR. Set Reset bit, all control registers assume their reset values. Note1 16 tSCYCLE delay until CLRR Note2 command. 0100 - SETF. Set fast (normal) clock mode. 4 tSCYCLE delay until next command. 1011 - CLRR. Clear Reset bit, all control registers retain their reset values. Note1 4 tSCYCLE delay until next command. 1111 - NOP. No serial operation. 0011, 0101 - 1010, 1100 - 1110 - RSRV. Reserved encodings. SDEV5..SDEV0 SBC SA11..SA0 SD15..SD0 Serial device. Compared to SDEVID5..SDEVID0 field of INIT control register field to select the RDRAM device to which the transaction is directed. Serial broadcast. When set, RDRAM devices ignore {SDEV5..SDEV0} for RDRAM device selection. Serial address. Selects which control register of the selected RDRAM device is read or written. Serial data. The 16 bits of data written to or read from the selected control register of the selected RDRAM device.
Notes 1 The SETR and CLRR commands must always be applied in two successive transactions to RDRAM devices; i.e. they may not be used in isolation. This is called "SETR/CLRR Reset". 2 A minimum gap equal to the larger of (16*tSCYCLE, 2816*tCYCLE) must be inserted between a SETR/CLRR command pair.
Preliminary Data Sheet E0260E40 (Ver. 4.0)
33
EDR2518ABSE
21. Initialization
Figure 21-1 SIO Pin Reset Sequence
T0 SCK 0 1 CMD
00001100
T 16 1
00000000...00000000
0 1 SIO0
0000000000000000
The packet is repeated from SIO0 to SIO1 SIO1
0000000000000000
0 1 0
Initialization refers to the process that a controller must go through after power is applied to the system or the system is reset. The controller prepares the RDRAM sub-system for normal Channel operation by (primarily) using a sequence of control register transactions on the serial CMOS pins. The following steps outline the sequence seen by the various memory subsystem components (including the RDRAM components) during initialization. This sequence is available in the form of reference code. Contact Rambus Inc. for more information. 1.0 Start Clocks This step calculates the proper clock frequencies for PClk (controller logic), SynClk (RAC block), RefClk (DRCG component), CTM (RDRAM component), and SCK (SIO block). 2.0 RAC Initialization This step causes the INIT block to generate a sequence of pulses which resets the RAC, performs RAC maintainance operations, and measures timing intervals in order to ensure clock stability. 3.0 RDRAM device Initialization This stage performs most of the steps needed to initialize the RDRAM devices. The rest are performed in stages 5.0, 6.0, and 7.0. All of the steps in 3.0 are carried out through the SIO block interface. 3.1/3.2 SIO Reset This reset operation is performed before any SIO control register read or write transactions. It clears six registers (TEST34, CCA, CCB, SKIP, TEST78, and TEST79) and places the INIT register into a special state (all bits cleared except SKP and SDEVID fields are set to ones). SCK must be held low until SIO Reset. 3.3 Write TEST77 Register The TEST77 register must be explicitly written with zeros before any other registers are read or written. 3.4 Write TCYCLE Register The TCYCLE register is written with the cycle time tCYCLE of the CTM clock (for Channel and RDRAM devices) in units of 64ps. The tCYCLE value is determined in stage 1.0. 3.5 Write SDEVID Register The SDEVID (serial device identification) register of each RDRAM device is written with a unique address value so that directed SIO read and write transactions can be performed. This address value increases from 0 to 31 according to the distance an RDRAM device is from the ASIC component on the SIO bus (the closest RDRAM device is address 0). 34
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
3.6 Write DEVID Register The DEVID (device identification) register of the RDRAM device is written with a unique address value so that directed memory read and write transactions can be performed. This address value increases from 0 to 31. The DEVID value is not necessarily the same as the SDEVID value. RDRAM devices are sorted into regions of the same core configuration (number of bank, row, and column address bits and core type). 3.7 Write PDNX, PDNXA Registers The PDNX and PDNXA registers are written with values that are used to measure the timing intervals connected with an exit from the PDN (powerdown) power state. 3.8 Write NAPX Register The NAPX register is written with values that are used to measure the timing intervals connected with an exit from the NAP power state. 3.9 Write TPARM Register The TPARM register is written with values which determine the time interval between a COL packet with a memory read command and the Q packet with the read data on the Channel. The values written set the RDRAM to the minimum value permitted for the system. This will be adjusted later in stage 6.0. 3.10 Write TCDLY1 Register The TCDLY1 register is written with values which determine the time interval between a COL packet with a memory read command and the Q packet with the read data on the Channel. The values written set the RDRAM to the minimum value permitted for the system. This will be adjusted later in stage 6.0. 3.11 Write TFRM Register The TFRM register is written with a value that is related to the tRCD parameter for the system. The tRCD parameter is the time interval between a ROW packet with an activate command and the COL packet with a read or write command. 3.12 SETR/CLRR Each RDRAM device is given a SETR command and a CLRR command through the SIO block. This sequence performs a second reset operation on the RDRAM devices. 3.13 Write CCA and CCB Registers These registers are written with a value halfway between their minimum and maximum values. This shortens the time needed for the RDRAM devices to reach their steady-state current control values in stage 5.0. 3.14 Powerdown Exit The RDRAM devices are in the PDN power state at this point. A broadcast PDNExit command is performed by the SIO block to place the RDRAM devices in the RLX (relax) power state in which they are ready to receive ROW packets. 3.15 SETF Each RDRAM device is given a SETF command through the SIO block. One of the operations performed by this step is to generate a value for the AS (autoskip) bit in the SKIP register and fix the RDRAM device to a particular read domain.
Preliminary Data Sheet E0260E40 (Ver. 4.0)
35
EDR2518ABSE
4.0 Controller Configuration This stage initializes the controller block. Each step of this stage will set a field of the ConfigRMC[63:0] bus to the appropriate value. Other controller implementations will have similar initialization requirements, and this stage may be used as a guide. 4.1 Initial Read Data Offset The ConfigRMC bus is written with a value which determines the time interval between a COL packet with a memory read command and the Q packet with the read data on the Channel. The value written sets RMC.d1 to the minimum value permitted for the system. This will be adjusted later in stage 6.0. 4.2 Configure Row/Column Timing This step determines the values of the tRAS,MIN , tRP,MIN , tRC,MIN , tRCD,MIN , tRR,MIN , and tPP,MIN RDRAM timing parameters that are present in the system. The ConfigRMC bus is written with values that will be compatible with all RDRAM devices that are present. 4.3 Set Refresh Interval This step determines the values of the tREF,MAX RDRAM timing parameter that are present in the system. The ConfigRMC bus is written with a value that will be compatible with all RDRAM devices that are present. 4.4 Set Current Control Interval This step determines the values of the tCCTRL,MAX RDRAM timing parameter that are present in the system. The ConfigRMC bus is written with a value that will be compatible with all RDRAM devices that are present. 4.5 Set Slew Rate Control Interval This step determines the values of the tTEMP,MAX RDRAM timing parameter that are present in the system. The ConfigRMC bus is written with a value that will be compatible with all RDRAM devices that are present. 4.6 Set Bank/Row/Col Address Bits This step determines the number of RDRAM bank, row, and column address bits that are present in the system. It also determines the RDRAM core types (independent, doubled, or split) that are present. The ConfigRMC bus is written with a value that will be compatible with all RDRAM devices that are present. 5.0 RDRAM Current Control This step causes the INIT block to generate a sequence of pulses which performs RDRAM maintenance operations. 6.0 RDRAM Core, Read Domain Initialization This stage completes the RDRAM device initialization 6.1 RDRAM Core Initialization A sequence of 192 memory refresh transactions is performed in order to place the cores of all RDRAM devises into the proper operating state. 6.2 RDRAM Read Domain Initialization A memory write and memory read transaction is performed to each RDRAM device to determine which read domain each RDRAM device occupies. The programmed delay of each RDRAM device is then adjusted so the total RDRAM read delay (propagation delay plus programmed delay) is constant. The TPARM and TCDLY1 registers of each RDRAM device are rewritten with the appropriate read delay values. The ConfigRMC bus are also rewritten with an updated value. 36
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
7.0 Other RDRAM Register Fields This stage rewrites the INIT register with the final values of the LSR, NSR, and PSR fields. In essence, the controller must read all the read-only configuration registers of all RDRAM devices (or it must read the SPD device present on each RIMM), it must process this information, and then it must write all the readwrite registers to place the RDRAM devices into the proper operating mode. Initialization Note : 1. During the initialization process, it is necessary for the controller to perform 128 current control operations (3xCAL, 1xCAL/SAM) and one temperature calibrate operation (TCEN/TCAL) after reset or after powerdown (PDN) exit. 2. The behavior of EDR2518ABSE at initialization is as follows. It is distinguished by the "S28IECO" bit in the SPD. S28IECO=1: Upon powerup, the device enters PDN state. The serial operations SETR, CLRR, and SETF require a SDEVID match. See the document detailing the reference initialization procedure for more information on how to handle this in a system. 3. After the step of equalizing the total read delay of the RDRAM device has been completed (i.e. after the TCDLY0 and TCDLY1 fields have been written for the final time), a single final memory read transaction should be made to the RDRAM device in order to ensure that the output pipeline stages have been cleared. 4. The SETF command (in the serial SRQ packet) should only be issued once during the Initialization process, as should the SETR and CLRR commands. 5. The CLRR command (in the serial SRQ packet) leaves some of the contents of the memory core in an indeterminate state.
Preliminary Data Sheet E0260E40 (Ver. 4.0)
37
EDR2518ABSE
22. Control Register Summary
Table 22-1 summarizes the RDRAM control registers. Detail is provided for each control register in Figure 22-1. Read-only bits which are shaded gray are unused and return zero. Read-write bits which are shaded gray are reserved and should always be written with zero. The RIMM SPD Application Note (DL-0054) of Rambus Inc. describes additional read-only configuration registers which are present on Direct RIMMs. The state of the register fields are potentially affected by the IO Reset operation or the SETR/CLRR operation. This is indicated in the text accompanying each register diagram. Table 22-1 Control Register Summary (1/2)
SA11..SA0 02116 Register INIT Field SDEVID PSX SRP NSR PSR LSR X DIS IDM 02216 02316 TEST34 CNFGA TEST34 REFBIT DBL MVER PVER 02416 CNFGB BYT DEVTYP read-write/ read-only read-write, 6 bits read-write, 1 bit read-write, 1 bit read-write, 1 bit read-write, 1 bit read-write, 1 bit read-only, 1 bit read-write, 1 bit read-write, 1 bit read-write, 16 bits read-only, 3 bits read-only, 1 bit read-only, 6 bits read-only, 6 bits read-only, 1 bit read-only, 3 bits read-only, 1 bit read-only, 6 bits read-only, 6 bits read-write, 5 bits read-write, 4 bits read-write, 9 bits read-write, 7 bits read-write, 2 bits read-write, 7 bits read-write, 2 bits read-write, 5 bits read-write, 5 bits read-write, 1 bit read-write, 13 bits Description Serial device ID. Device address for control register read/write. Power select exit. PDN/NAP exit with device addr on DQA5..0. SIO repeater. Used to initialize RDRAM devices. NAP self-refresh. Enables self-refresh in NAP mode. PDN self-refresh. Enables self-refresh in PDN mode. Low power self-refresh. Enables low power self-refresh. Output undefined RDRAM device disable. Interleaved Device Mode enable. IDM = 0 for version 3 device. Test register. Refresh bank bits. Used for multi-bank refresh. Double. Specifies doubled-bank architecture. Manufacturer version. Manufacturer identification number. Protocol version. Specifies version of Direct protocol supported. Byte. Specifies an 8-bit or 9-bit byte size. Device type. Device can be RDRAM device or some other device category. SPT CORG SVER 04016 04116 04216 04316 DEVID REFB REFR CCA DEVID REFB REFR CCA ASYMA 04416 CCB CCB ASYMB 04516 NAPX NAPXA NAPX DQS 04616 PDNXA PDNXA Split-core. Each core half is an individual dependent core. Core organization. Bank, row, column address field sizes. Stepping version. Mask version number. Device ID. Device address for memory read/write. Refresh bank. Next bank to be refreshed by self-refresh. Refresh row. Next row to be refreshed by REFA, self-refresh. Current control A. Controls IOL output current for DQA. Asymmetry control. Controls asymmetry of VOL/VOH swing for DQA. Current control B. Controls IOL output current for DQB. Asymmetry control. Controls asymmetry of VOL/VOH swing for DQB. NAP exit. Specifies length of NAP exit phase A. NAP exit. Specifies length of NAP exit phase A + phase B. DQ select. Selects CMD framing for NAP/PDN exit. PDN exit. Specifies length of PDN exit phase A.
38
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
Table 22-1 Control Register Summary (2/2)
SA11..SA0 Register 04716 04816 PDNX TPARM Field PDNX TCAS TCLS TCDLY0 04916 04a16 04c16 04b16 TFRM TFRM read-write/ read-only read-write, 13 bits read-write, 2 bits read-write, 2 bits read-write, 3 bits read-write, 4 bits read-write, 3 bits read-write, 14 bits read-only, 1 bit read-write, 1 bit read-write, 1 bit read-write, 16 bits read-write, 16 bits read-write, 16 bits read-write, 2bits vendor-specific Description PDN exit. Specifies length of PDN exit phase A + phase B. tCAS-C core parameter. Determines tOFFP datasheet parameter. tCLS-C core parameter. Determines tCAC and tOFFP parameters. tCDLY0-C core parameter. Programmable delay for read data. tFRM-C core parameter. Determines ROW - COL packet framing interval.
TCDLY1 TCDLY1 TCYCLE TCYCLE SKIP AS MSE MS
tCDLY-1 core parameter. Programmable delay for read data.
tCYCLE datasheet parameter. Specifies cycle time in 64ps units. Autoskip value established by the SETF command. Manual skip enable. Allows the MS value to override the AS value. Manual skip value. Test register. Write with zero after SIO reset. Test register. Do not read or write after SIO reset. Test register. Do not read or write after SIO reset. tCPS-C core parameter. Determines tOFFP parameters. (Version 3 only) Vendor-specific test registers. Do not read or write after SIO reset.
04d1604e1604f1605516 08016-Off16
TEST77 TEST77 TEST78 TEST78 TEST79 TEST79 TCPS TCPS
reserved reserved
Preliminary Data Sheet E0260E40 (Ver. 4.0)
39
EDR2518ABSE
Figure 22-1 Control Registers (1/7)
Control Register : INIT
15 IDM 14 SDE VID5 13 DIS 12 X
Note
Address : 02116
10 9 PSR 8 NSR 7 SRP 6 PSX 5 0 4 3 2 SDEVID4..0 1 0
11 0
LSR
Read/write register. Reset values are undefined except as affected by SIO Reset as noted below. SETR/CLRR Reset does not affect this register. Note Read-only bit. Output undefined. Field IDM Description Reset value
Interleaved Device Mode enable. IDM = 0 for version 3 device.
3f16
SDEVID5..0 Serial Device Identification. Compared to SDEVID5..0 serial address field of serial request packet for register read/write transactions. This determines which RDRAM device is selected for the register read or write operation. DIS LSR PSR NSR SRP PSX RDRAM disable. DIS=1 causes RDRAM device to ignore NAP/PDN exit sequence, DIS=0 permit normal operation. This mechanism disables an RDRAM device. Low Power Self-Refresh. This function is not supported. LSR value must be 0. PDN Self-Refresh. PSR=1 enables self-refresh in PDN mode. PSR can't be set while in PDN mode. NAP Self-Refresh. NSR=1 enables self-refresh in NAP mode. NSR can't be set while in NAP mode. SIO Repeater. Controls value on SIO1; SIO1=SIO0 if SRP=1, SIO1=1 if SRP=0. Power Exit Select. PDN and NAP are exited with (=0) or without (=1) a device address on the DQA5..0 pins. PDEV5 (on DQA5) selectes broadcast (1) or directed (0) exit. For a dircted exit, PDEV4..0 (on DQA4..0) is compared to DEVID4..0 to select a device.
0 0 0 0 1
Control Register : CNFGA
15 14 13 12 11 10 9 PVER5..0=000001
Address : 02316
8 7 6 5 4 3 DBL1 2 1 0 MVER5..0=mmmmmm REFBIT2..0=101
Read only register. Field PVER5..0 Description Protocol Version. Specifies the Direct Protocol version used by this device: 0 - Reserved 1 - Version 1 2 - Version 2 (version 1 + IDM) 3 - Version 3 (version 1 + programmable tCPS) Manufacturer Version. Specifies the manufacturer identification number. Doubled-Bank. DBL=1 means the device uses a doubled-bank architecture with adjacent-bank dependency. DBL=0 means no dependency.
MVER5..0 DBL
REFBIT2..0 Refresh Bank Bits. Specifies the number of bank address bits used by REFA and REFP commands. Permits multi-bank refresh in future RDRAM devices. Caution In RDRAM devices with protocol version 1 PVER[5:0] =000001, the range of the PDNX field (PDNX[2:0] in the PDNX register) may not be large enough to specify the location of the restricted interval in Figure 23-3. In this case, the effective tS4 parameter must increase and no row or column packets may overlap the restricted interval. See Figure 23-3 and Timing conditions table.
40
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
Figure 22-1 Control Registers (2/7)
Control Register : CNFGB
15 14 13 12 11 10 9 SVER5..0=ssssss
Address : 02416
8 7 6 5 4 SPT0 3 2 1 0 BYTB CORG4..0=01000 DEVTYP2..0=000
Read only register. Field SVER5..0 CORG4..0 SPT Description Stepping version. Specifies the mask version number of this device. Core organization. This field specifies the number of bank (5 bits), row (9 bits), and column (7 bits) address bits. Split-core. SPT=1 means the core is split, SPT=0 means it is not.
DEVTYP2..0 Device type. DEVTYP=000 means that this device is an RDRAM device. BYT Byte width. B=1 means the device reads and writes 9-bit memory bytes.B=0 means 8 bits.
Control Register : TEST34
15 0 14 0 13 0 12 0 11 0 10 0 9 0
Address : 02216
8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Write only register. Reset values of TEST34 is zero (from SIO Reset). This register are used for testing purposes. It must not be read or written after SIO Reset.
Control Register : DEVID
15 0 14 0 13 0 12 0 11 0 10 0 9 0
Address : 04016
8 0 7 0 6 0 5 0 4 3 2 DEVID4..0 1 0
Read/write register. Reset value is undefined. Field DEVID4..0 Description Device Identification register. DEVID4..DEVID0 is compared to DR4..DR0, DC4..DC0, and DX4..DX0 fields for all memory read or write transactions. This determines which RDRAM device is selected for the memory read or write transaction.
Preliminary Data Sheet E0260E40 (Ver. 4.0)
41
EDR2518ABSE
Figure 22-1 Control Registers (3/7)
Control Register : REFB
15 0 14 0 13 0 12 0 11 0 10 0 9 0
Address : 04116
8 0 7 0 6 0 5 0 4 3 2 REFB4..0 1 0
Read/write register. Field REFB4..0 Description Reset value is zero (from SETR/CLRR). Refresh Bank Register. REFB4..REFB0 is the bank that will be refreshed next during self-refresh. REFB4..0 is incremented after each self-refresh activate and precharge operation pair. Reset value 0
Control Register : REFR
15 0 14 0 13 0 12 0 11 0 10 0 9 0
Address : 04216
8 7 6 5 4 REFR8..0 3 2 1 0
Read/write register. Field REFR8..0 Description Reset value is zero (from SETR/CLRR). Refresh Row register. REFR8..REFR0 is the row that will be refreshed next by the REFA command or by self-refresh. REFR8..0 is incremented when BR4..0=11111 for the REFA command. REFR8..0 is incremented when REFB4..0=11111 for self-refresh. Reset value 0
Control Register : CCA
15 0 14 0 13 0 12 0 11 0 10 0 9 0
Address : 04316
8 0 7 ASYM A0 6 5 4 3 CCA6..0 2 1 0
Read/write register. Reset value is zero (from SETR/CLRR or SIO Reset). Field ASYMA0 Description ASYMA0 control the asymmetry of the VOL/VOH voltage swing about the VREF reference voltage for the DQA8..0 pins. Current Control A. Controls the IOL output current for the DQA8..DQA0 pins. Reset value 0
CCA6..0
Control Register : CCB
15 0 14 0 13 0 12 0 11 0 10 0 9 0
Address : 04416
8 0 7 ASYM B0 6 5 4 3 CCB6..0 2 1 0
Read/write register. Reset value is zero (from SETR/CLRR or SIO Reset). Field ASYMB0 CCB6..0 Description ASYMB0 control the asymmetry of the VOL/VOH voltage swing about the VREF reference voltage for the DQB8..0 pins. Current Control B. Controls the IOL output current for the DQB8..DQB0 pins. Reset value 0
42
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
Figure 22-1 Control Registers (4/7)
Control Register : NAPX
15 0 14 0 13 0 12 0 11 0 10 DQS 9
Address : 04516
8 7 NAPX4..0 6 5 4 3 2 NAPXA4..0 1 0
Read/write register. Reset value is 052516 (SIOReset). Note tSCYCLE is tCYCLE1 (SCK cycle time). Field DQS Description DQ Select. This field specifies the number of SCK cycles (0 0.5 cycles, 1 1.5 cycles) between the CMD pin framing sequence and the device selection on DQ5..0. see Figure 23-4. This field must be written with a "1" for this RDRAM. Nap Exit Phase A plus B. This field specifies the number of SCK cycles during the first plus second phases for exiting NAP mode. It must satisfy: NAPX*tSCYCLE NAPXA*tSCYCLE+tNAPXB,MAX Do not set this field to zero. Nap Exit Phase A. This field specifies the number of SCK cycles during the first phase for exiting NAP mode. It must satisfy: NAPXA*tSCYCLE tNAPXA,MAX Do not set this field to zero.
NAPX4..0
NAPXA4..0
Control Register : PDNXA
15 0 14 0 13 0 12 11 10 9
Address : 04616
8 7 6 PDNXA12..0 5 4 3 2 1 0
Read/write register. Reset value is 000816 (SIOReset). Field PDNXA4..0 Description PDN Exit Phase A. This field specifies the number of (64*SCK cycle) units during the first phase for exiting PDN mode. It must satisfy: PDNXA*64*tSCYCLE tPDNXA,MAX Do not set this field to zero. Note - only PDNXA4..0 are implemented. Note - tSCYCLE is tCYCLE1 (SCK cycle time).
Control Register : PDNX
15 0 14 0 13 0 12 11 10 9
Address : 04716
8 7 6 PDNX12..0 5 4 3 2 1 0
Read/write register. Reset value is 000716 (SIOReset). Field PDNX2..0 Description PDN Exit Phase A puls B. This field specifies the number of (256*SCK cycle) units during the first plus second phases for exiting PDN mode. It should satisfy: PDNX*256*tSCYCLE PDNXA*64*tSCYCLE+tPDNXB,MAX It this equation can't be satisfied, then the maximum PDNX value should be written, and the tS4 / tH4 timing window will be modified (see Figure 23-4). Do not set this field to zero. Note - only PDNX2..0 are implemented. Note - tSCYCLE is tCYCLE1 (SCK cycle time).
Preliminary Data Sheet E0260E40 (Ver. 4.0)
43
EDR2518ABSE
Figure 22-1 Control Registers (5/7)
Control Register : TPARM
15 0 14 0 13 0 12 0 11 0 10 0 9 0
Address : 04816
8 0 7 0 6 5 TCDLY0 4 3 TCLS 2 1 TCAL 0
Read/write register. Reset value is undefined. Field TCDLY0 Description Specifies the tCDLY0-C core parameter in tCYCLE units. This adds a programmable delay to Q (read data) packets, permitting round trip read delay to all device to be equalized. This field may be written with the values "011" (3*tCYCLE) through "101" (5*tCYCLE). Specifies the tCLS-C core parameter in tCYCLE units. Should be "10" (2*tCYCLE).
TCLS1..0
Specifies the tCAS-C core parameter in tCYCLE units. This should be "10" (2*tCYCLE). TCAS1..0 The equations relating the core parameters to the datasheet parameters follow: tCAS-C=2*tCYCLE tCLS-C=2*tCYCLE tCPS-C=1*tCYCLE tOFFP=tCPS-C + tCAS-C + tCLS-C - 1*tCYCLE =4*tCYCLE tRCD=tRCD-C + 1*tCYCLE - tCLS-C =tRCD-C - 1*tCYCLE tCAC=3*tCYCLE + tCLS-C + tCDLY0-C + tCDLY1-C (see table below programming ranges) TCDLY0 011 011 100 011 100 100 101 tCDLY0-C 3*tCYCLE 3*tCYCLE 4*tCYCLE 3*tCYCLE 4*tCYCLE 4*tCYCLE 5*tCYCLE TCDLY1 000 001 000 010 001 010 010 tCDLY1-C 0*tCYCLE 1*tCYCLE 0*tCYCLE 2*tCYCLE 1*tCYCLE 2*tCYCLE 2*tCYCLE tCAC@tCYCLE=2.50 ns 8*tCYCLE 9*tCYCLE 9*tCYCLE 10*tCYCLE 10*tCYCLE 11*tCYCLE 12*tCYCLE tCAC@tCYCLE=1.875 ns 8*tCYCLE
Note
not allowed
9*tCYCLE
not allowed
10*tCYCLE 11*tCYCLE 12*tCYCLE
Note Used only for device bins that support tCAC = 8
Control Register : TFRM
15 0 14 0 13 0 12 0 11 0 10 0 9 0
Address : 04916
8 0 7 0 6 0 5 0 4 0 3 2 1 0 TFRM3..0
Read/write register. Reset value is undefined. Field TFRM3..0 Description Specifies the position of the framing point in tCYCLE units. This value must be greater than or equal to the tFRM,MIN parameter. This is the minimum offset between a ROW packet (which places a device at ATTN) and the first COL packet (directed to that device) which must be framed. This field may be written with the value "0111" (7*tCYCLE) through "1010" (10*tCYCLE). TFRM is usually set to the value which matches the largest tRCD,MIN parameter (modulo 4*tCYCLE) that is present in an RDRAM device in the memory system. Thus, if an RDRAM device with tRCD,MIN=11*tCYCLE were present, then TFRM would be programmed to 7*tCYCLE.
44
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
Figure 22-1 Control Registers (6/7)
Control Register : TCDLY1
15 0 14 0 13 0 12 0 11 0 10 0 9 0
Address : 04a16
8 0 7 0 6 0 5 0 4 0 3 0 2 1 TCDLY1 0
Read/write register. Reset value is undefined. Field TCDLY1 Description Specifies the value of the tCDLY1-C core parameter in tCYCLE units. This adds a programmable delay to Q (read data) packets, permitting round trip read to delay all devices to be equalized. This field may be written with the values "000" (0*tCYCLE) through "010" (2*tCYCLE). Refer to TPARM Register for more details.
Control Register : SKIP
15 0 14 0 13 0 12 AS 11 MSE 10 MS 9 0
Address : 04b16
8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Read/write register (except AS field). Reset value is zero (SIO Reset). Field MS MSE AS Description Manual skip (MS=1 corresponds to the early Q(a1) packet and AS=0 to the Q(a1) packet one tCYCLE later for the four uncertain cases in Figure34-1.). Manual skip enable (0=auto, 1=manual ). Autoskip. Read-only value determined by autoskip circuit and stored when SETF serial command is received by RDRAM during initialization. In Figure34-1, AS=1 corresponds to the early Q(a1) packet and AS=0 to the Q(a1) packet one tCYCLE later for the four uncertain cases.
Control Register : TCYCLE
15 0 14 0 13 12 11 10 9
Address : 04c16
8 7 6 5 4 3 2 1 0 TCYCLE13..0
Read/write register. Reset value is undefined. Field TCYCLE13..0 Description Specifies the value of the tCYCLE datasheet parameter in 64ps units. For the tCYCLE,MIN of 2.50 ns (2500ps), this field should be written with the value "0002716" (39*64ps).
Preliminary Data Sheet E0260E40 (Ver. 4.0)
45
EDR2518ABSE
Figure 22-1 Control Registers (7/7)
Control Register : TEST77 Control Register : TEST78 Control Register : TEST79
15 0 14 0 13 0 12 0 11 0 10 0 9 0
Address : 04d16 Address : 04e16 Address : 04f16
8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Read/write register. These registers must only be used for testing purposes. Field TEST77 TEST78 TEST79 Description It must be written with zero after SIO reset. Reset value is zero (SIO Reset). Do not read or written after SIO reset. Reset value is zero (SIO Reset). Do not read or written after SIO reset. Reset value 0 0
Control Register : TCPS
15 0 14 0 13 0 12 0 11 0 10 0 9 0
Address : 05516
8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 TCPS 0
Read/write register Reset value is 000116 (SETR/CLRR). Field TCPS Description Specifies the value pf the tCPS-C core parameter in tCYCLE units. This adds a programmable delay to tOFFP. This field may be written with the values "01" (1*tCYCLE) through "11" (3*tCYCLE). Refer to the Figure 22-1 (5/7).
Note This register is implemented (as stated above) in a version 3 device and unimplemented in a version 1, 2 device.
46
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
23. Power State Management
Table 23-1 summarizes the power states available to an RDRAM device. In general, the lowest power states have the longest operational latencies. For example, the relative power levels of PDN state and STBY state have a ratio of about 1:110, and the relative access latencies to get read data have a ratio of about 250:1. PDN state is the lowest power state available. The information in the RDRAM core is usually maintained with selfrefresh; an internal timer automatically refreshes all rows of all banks. PDN has a relatively long exit latency because the TCLK/RCLK block must resynchronize itself to the external clock signal. NAP state is another low-power state in which either self-refresh or REFA-refresh are used to maintain the core. See 24. Refresh for a description of the two refresh mechanisms. NAP has a shorter exit latency than PDN because the TCLK/RCLK block maintains its synchronization state relative to the external clock signal at the time of NAP entry. This imposes a limit (tNLIMIT) on how long an RDRAM device may remain in NAP state before briefly returning to STBY or ATTN to update this synchronization state. Table 23-1 Power State Summary
Power State Description PDN Powerdown state. Blocks consuming power Power state Self-refresh NAP Description Nap state. Similar to PDN except lower wake-up latency. Attention state. Ready for ROW and COL packets. Attention write state. Ready for ROW and COL packets. Ready for D (write data) packets. Blocks consuming power Self-refresh or REFA-refresh TCLK/RCLK-Nap REFA-refresh TCLK/RCLK ROW demux receiver COL demux receiver REFA-refresh TCLK/RCLK ROW demux receiver COL demux receiver DQ demux receiver Core power
STBY
Standby state. Ready for ROW packets. Attention read state. Ready for ROW and COL packets. Sending Q (read data) packets.
REFA-refresh TCLK/RCLK ROW demux receiver REFA-refresh TCLK/RCLK ROW demux receiver COL demux receiver DQ mux transmitter Core power
ATTN
ATTNR
ATTNW
Preliminary Data Sheet E0260E40 (Ver. 4.0)
47
EDR2518ABSE
Figure 23-1 summarizes the transition conditions needed for moving between the various power states.
Figure 23-1 Power State Transition Diagram
automatic
ATTNR
automatic
automatic automatic
ATTNW
automatic automatic
ATTN
PDNR NAPR RLX
tNLIMIT NAPR NAPR PDEV.CMD*SIO0
NAP
PDNR PDNR
PDN
PDNR
ATTN
NAPR
PDEV.CMD*SIO0 SETR/CLRR
STBY
Notation: SETR/CLRR - SETR/CLRR Reset sequence in SRQ packet PDNR - PDNR command in ROWR packet NAPR - NAPR command in ROWR packet RLXR - RLX command in ROWR packet RLX - RLX command in ROWR,COLC,COLX packets SIO0 - SIO0 input value PDEV.CMD - (PDEV=DEVID)*(CMD=01) ATTN - ROWA packet(non-broadcast) or ROWR packet (non-broadcast) with ATTN command
At initialization, the SETR/CLRR Reset sequence will put the RDRAM device into PDN state. The PDN exit sequence involves an optional PDEV specification and bits on the CMD and SIOIN pins. Once the RDRAM device is in STBY, it will move to the ATTN/ATTNR/ATTNW states when it receives a nonbroadcast ROWA packet or non-broadcast ROWR packet with the ATTN command. The RDRAM device returns to STBY from these three states when it receives a RLX command. Alternatively, it may enter NAP or PDN state from ATTN or STBY states with a NAPR or PDNR command in an ROWR packet. The PDN or NAP exit sequence involves an optional PDEV specification and bits on the CMD and SIO0 pins. The RDRAM device returns to the STBY state it was originally in when it first entered NAP or PDN. An RDRAM device may only remain in NAP state for a time tNLIMIT. It must periodically return to ATTN or STBY. The NAPRC command causes a napdown operation if the RDRAM device's NCBIT is set. The NCBIT is not directly visible. It is undefined on reset. It is set by a NAPR command to the RDRAM device, and it is cleared by an ACT command to the RDRAM device. It permits a controller to manage a set of RDRAM devices in a mixture of power states. STBY state is the normal idle state of the RDRAM device. In this state all banks and sense amps have usually been left precharged and ROWA and ROWR packets on the ROW pins are being monitored. When a non-broadcast ROWA packet or non-broadcast ROWR packet(with the ATTN command) packet addressed to the RDRAM device is seen, the RDRAM device enters ATTN state (see the right side of Figure 23-2). This requires a time tSA during which the RDRAM device activates the specified row of the specified bank. A time TFRM*tCYCLE after the ROW packet, the RDRAM device will be able to frame COL packets (TFRM is a control register field - see Figure 22-1(5/7) "TFRM Register"). Once in ATTN state, the RDRAM device will automatically transition to the ATTNW and ATTNR states as it receives WR and RD commands.
48
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
Once the RDRAM device is in ATTN, ATTNW, or ATTNR states, it will remain there until it is explicitly returned to the STBY state with a RLX command. A RLX command may be given in an ROWR, COLC, or COLX packet (see the left side of Figure 23-2). It is usually given after all banks of the RDRAM device have been precharged; if other banks are still activated, then the RLX command would probably not be given. If a broadcast ROWA packet or ROWR packet (with the ATTN command) is received, the RDRAM device's power state doesn't change. If a broadcast ROWR packet with RLXR command is received, the RDRAM device goes to STBY. Figure 23-2 STBY Entry (left) and STBY Exit (right)
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T 20T 21 T 22 T23 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16 0
CTM/CFM ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0 t AS
RLXR
CTM/CFM ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0 t SA STBY Power State
STBY ATTN
ROP=non-broadcast ROWA or ROWR/ATTN a0={d0, b0, r0} a1={d1, b1, c1}
ROP a0 COP a1 COP a1 COP a1 COP a1 COP a0 XOP a1 XOP a0
RLXC RLXX
No COL packets may be placed in the three indicated positions; i.e. at (TFRM-{1,2,3})*tCYCLE. A COL packet to device d0 (or any other device) is okay at (TFRM)*tCYCLE or later. A COL packet to another device (d1!=d0) is okay at (TFRM-4)*tCYCLE or earlier.
TFRM*tCYCLE
Power State
ATTN
Figure 23-3 shows the NAP entry sequence (left). NAP state is entered by sending a NAPR command in a ROW packet. A time tASN is required to enter NAP state (this specification is provided for power calculation purposes). The clock on CTM/CFM must remain stable for a time tCD after the NAPR command. Figure 23-3 NAP Entry (left) and PDN Entry (right)
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T 20T 21 T 22 T23 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 0
CTM/CFM
CTM/CFM
a0={d0, b0, r0, c0} a1={d1, b1, c1, c1}
t CD
ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0 t ASN Power State ATTN/STBY Note NAP Power State
ROP a0
(NAPR)
t CD
ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0
ROP a0
(PDNR)
restricted
ROP a1
restricted
ROP a1
t NPQ
COP a0 XOP a0 restricted COP a1 XOP a1
tNPQ
COP a0 XOP a0 restricted COP a1 XOP a1
No ROW or COL packets directed to device d0 may overlap the restricted interval. No broadcast ROW packets may overlap the quiet interval.
ROW or COL packets to a device other than d0 may overlap the restricted interval.
t ASP
ATTN/STBY Note
ROW or COL packets directed to device d0 after the restricted interval will be ignored.
PDN
Note The(eventual) NAP/PDN exit will be to the same ATTN/STBY state the RDRAM was in prior to NAP/PDN entry
The RDRAM device may be in ATTN or STBY state when the NAPR command is issued. When NAP state is exited, the RDRAM device will return to the STBY. After a NAP exit, the RDRAM device may consume power as if it is in ATTN state until a RLX command is received. Figure 23-3 also shows the PDN entry sequence (right). PDN state is entered by sending a PDNR command in a ROW packet. A time tASP is required to enter PDN state (this specification is provided for power calculation purposes). The clock on CTM/CFM must remain stable for a time tCD after the PDNR command.
Preliminary Data Sheet E0260E40 (Ver. 4.0)
49
EDR2518ABSE
The RDRAM device may be in ATTN or STBY state when the PDNR command is issued. When PDN state is exited, the RDRAM device will return to the STBY. After a PDX exit, the RDRAM device may consume power as if it is in ATTN state until a RLX command is received. Also, the current- and slew-rate-control levels are re-established. The RDRAM device's write buffer must be retired with the appropriate COP command before NAP or PDN are entered. Also, all the RDRAM device's banks must be precharged before NAP or PDN are entered. The exception to this is if NAP is entered with the NSR bit of the INIT register cleared (disabling self-refresh in NAP). The commands for relaxing, retiring, and precharging may be given to the RDRAM device as late as the ROPa0, COPa0, and XOPa0 packets in Figure 23-3. No broadcast packets nor packets directed to the RDRAM device entering NAP or PDN may overlay the quiet window. This window extends for a time tNPQ after the packet with the NAPR or PDNR command. Figure 23-4 shows the NAP and PDN exit sequences. These sequences are virtually identical; the minor differences will be highlighted in the following description. Before NAP or PDN exit, the CTM/CFM clock must be stable for a time tCE. Then, on a falling and rising edge of SCK, if there is a "01" on the CMD input, NAP or PDN state will be exited. Also, on the falling SCK edge the SIO0 input must be at a 0 for NAP exit and 1 for PDN exit. If the PSX bit of the INIT register is 0, then a device PDEV5..0 is specified for NAP or PDN exit on the DQA5..0 pins. This value is driven on the rising SCK edge 0.5 or 1.5 SCK cycles after the original falling edge, depending upon the value of the DQS bit of the NAPX register. If the PSX bit of the INIT register is 1, then the RDRAM device ignores the PDEV5..0 address packet and exits NAP or PDN when the wake-up sequence is presented on the CMD wire. The ROW and COL pins must be quiet at a time tS4 / tH4 around the indicated falling SCK edge(timed with the PDNX or NAPX register fields). After that, ROW and COL packets may be directed to the RDRAM device which is now in STBY state. Figure 23-5 shows the constraints for entering and exiting NAP and PDN states. On the left side, an RDRAM device exits NAP state at the end of cycle T3. This RDRAM device may not re-enter NAP or PDN state for an interval of tNU0. The RDRAM device enters NAP state at the end of cycle T13. This RDRAM device may not re-exit NAP state for an interval of tNU1. The equations for these two parameters depend upon a number of factors, and are shown at the bottom of the figure. NAPX is the value in the NAPX field in the NAPX register. On the right side of Figure23-4, an RDRAM device exits PDN state at the end of cycle T3. The RDRAM device may not re-enter PDN or NAP state for an interval of tPU0. The RDRAM device enters PDN state at the end of cycle T13 and may not re-exit PDN state for an interval of tPU1. The equations for these two parameters depend upon a number of factors, and are shown at the bottom of the figure. PDNX is the value in the PDNX field in the PDNX register.
50
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
Figure 23-4 NAP and PDN Exit
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T 20T 21 T 22 T 23 T 24T 25 T 26 T 27T 28T 29 T 30 T 31 T 32T 33 T 34 T 35 T 36T 37 T 38 T 39 T 40T 41 T 42 T 43T 44T 45 T 46 T 47
CTM/CFM ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0 SCK
If PSX=1 in Init register, then NAP/PDN exit is broadcast (no PDEV field). No ROW packets may overlap the restricted interval No COL packets may overlap the restricted interval if device PDEV is exiting the NAP or PDN states
ROP
restricted
ROP
t S4 tH4
COP XOP restricted COP XOP
t S3 t H3 t S3 t H3
Note 2 Note 2
tS4 tH4
t CE
PDEV5..0
PDEV5..0
Note 2 DQS=0 Note 2,3 DQS=1
CMD
0
1
SIO0
Note 1
0/1
The packet is repeated from SIO0 to SIO1
Effective hold becomes tH4' = tH4 +[PDNXA*64*tSCYCLE + tPDNXB,MAX] - [PDNX*256*tSCYCLE] if [PDNX*256*tSCYCLE] < [PDNXA*64*tSCYCLE + tPDNXB,MAX].
SIO1 Power State
Note 1
0/1
(NAPX*t SCYCLE )/(256*PDNX*t SCYCLE ) NAP/PDN
Note 2 Note 2
STBY/ATTN
DQS=0 DQS=1
Notes 1. Use 0 for NAP exit, 1 for PDN exit 2. Device selection timing slot is selected by DQS field of NAPX register. The PSX field determines the start of NAP/PDN exit. 3. The DQS field must be written with "1" for this RDRAM.
Figure 23-5 NAP Entry/Exit Windows (left) and PDN Entry/Exit Windows (right)
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T 20T 21 T 22 T 23 T 24T 25 T 26 T 27T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15T 16T 17 T 18 T 19
CTM/CFM
NAP entry
CTM/CFM
PDN entry
ROW2 ..ROW0
NAPR
ROW2 ..ROW0
PDNR
SCK
NAP exit
SCK
PDN exit 0 1
CMD
0
1
CMD
0
1
0
t NU0
no entry to NAP or PDN
t NU1
no exit
tPU0
t PU1
no entry to NAP or PDN no exit
tNU0 =5*t CYCLE +(2+NAPX)*t SCYCLE t NU1 =8*t CYCLE - (0.5*t SCYCLE ) =23*t CYCLE if NSR=0 if NSR=1
t PU0 =5*t CYCLE +(2+256*PDNX)*t SCYCLE t PU1 =8*t CYCLE - (0.5*t SCYCLE ) =23*t CYCLE if PSR=0 if PSR=1
Preliminary Data Sheet E0260E40 (Ver. 4.0)
51
EDR2518ABSE
24. Refresh
RDRAM devices, like any other DRAM technology, use volatile storage cells which must be periodically refreshed. This is accomplished with the REFA command. Figure 24-1 shows an example of this. The REFA command in the transaction is typically a broadcast command (DR4T and DR4F are both set in the ROWR packet), so that in all devices bank number Ba is activated with row number REFR, where REFR is a control register in the RDRAM device. When the command is broadcast and ATTN is set, the power state of the RDRAM devices (ATTN or STBY) will remain unchanged. The controller increments the bank address Ba for the next REFA command. When Ba is equal to its maximum value, the RDRAM device automatically increments REFR for the next REFA command. On average, these REFA commands are sent once every tREF / 2 BBIT+RBIT (where BBIT are the number of bank address bits and RBIT are the number of row address bits) so that each row of each bank is refreshed once every tREF interval. The REFA command is equivalent to an ACT command, in terms of the way that it interacts with other packets (see Table 6-1). In the example, an ACT command is sent after tRR to address b0, a different (non-adjacent) bank than the REFA command. A second ACT command can be sent after a time tRC to address c0, the same bank (or an adjacent bank) as the REFA command. Note that a broadcast REFP command is issued a time tRAS after the initial REFA command in order to precharge the refreshed bank in all RDRAM devices. After a bank is given a REFA command, no other core operations(activate or precharge) should be issued to it until it receives a REFP. It is also possible to interleave refresh transactions (not shown). In the figure, the ACT b0 command would be replaced by a REFA b0 command. The b0 address would be broadcast to all devices, and would be {Broadcast, Ba+2,REFR}. Note that the bank address should skip by two to avoid adjacent bank interference. A possible bank incrementing pattern would be: {12, 10, 5, 3, 0, 14, 9, 7, 4, 2, 13, 11, 8, 6, 1, 15, 28, 26, 21, 19, 16, 30, 25, 23, 20, 18, 29, 27, 24, 22, 17, 31}. Every time bank 31 is reached, a REFA command would automatically increment the REFR register. A second refresh mechanism is available for use in PDN and NAP power states. This mechanism is called selfrefresh mode. When the PDN power state is entered, or when NAP power state is entered with the NSR control register bit set, then self-refresh is automatically started for the RDRAM device. Self-refresh uses an internal time base reference in the RDRAM device. This causes an activate and precharge to be carried out once in every tREF / 2 BBIT+RBIT interval. The REFB and REFR control registers are used to keep track of the bank and row being refreshed. Before a controller places an RDRAM device into self-refresh mode, it should perform REFA/REFP refreshes until the bank address is equal to the last value (this will be 31 for all sequence). This ensures that no rows are skipped. Likewise, when a controller returns an RDRAM device to REFA/REFP refresh, it should start with the first bank address value (12 for the example sequence). Figure 24-2 illustrates the requirement imposed by the tBURST parameter. After PDN or NAP (when self-refresh is enabled) power states are exited, the controller must refresh all banks of the RDRAM device once during the interval tBURST after the restricted interval on the ROW and COL buses. This will ensure that regardless of the state of selfrefresh during PDN or NAP, the tREF, MAX parameter is met for all banks. During the tBURST interval, the banks may be refreshed in a single burst, or they may be scattered throughout the interval. Note that the first and last banks to be refreshed in the tBURST interval are numbers 12 and 31, in order to match the example refresh sequence.
52
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
Figure 24-1 REFA/REFP Refresh Transaction Example
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T 20T 21 T 22 T 23 T 24T 25 T 26 T 27T 28T 29 T 30 T 31 T 32T 33 T 34 T 35 T 36T 37 T 38 T 39 T 40T 41 T 42 T 43T 44T 45 T 46 T 47
CTM/CFM t RC ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0
Transaction a: REFA Transaction b: xx Transaction c: xx Transaction d: REFA a0 = {Broadcast,Ba,REFR} b0 = {Db, /={Ba,Ba+1,Ba-1}, Rb} c0 = {Dc, ==Ba, Rc} d0 = {Broadcast,Ba+1,REFR} a1 = {Broadcast,Ba} BBIT = #bank address bits RBIT = #row address bits REFB = REFB3..REFB0 REFR = REFR8..REFR0 REFA a0 ACT b0 REFP a1 ACT c0 REFA d0
t RAS
t RP
t RR tREF/2BBIT+RBIT
Figure 24-2 NAP/PDN Exit - tBURST Requirement
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T 20T 21 T 22 T 23 T 24T 25 T 26 T 27T 28T 29 T 30 T 31 T 32T 33 T 34 T 35 T 36T 37 T 38 T 39 T 40T 41 T 42 T 43T 44T 45 T 46 T 47
CTM/CFM
t BURST
ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0 SCK
ROP restricted ROP REFA b12 REFA b31
t S4 tH4
COP XOP restricted COP XOP
32 bank refresh sequence
tS4 tH4 t CE
CMD
0
1
SIO0
Note 1
0/1
The packet is repeated from SIO0 to SIO1
SIO1 Power State
Note 1
0/1
(NAPX*t SCYCLE )/(256*PDNX*t SCYCLE ) NAP/PDN
Note 2 Note 2
STBY
DQS=0 DQS=1
Notes 1. Use 0 for NAP exit, 1 for PDN exit 2. Device selection timing slot is selected by DQS field of NAPX register
Preliminary Data Sheet E0260E40 (Ver. 4.0)
53
EDR2518ABSE
25. Current and Temperature Control
Figure 25-1 shows an example of a transaction which performs current control calibration. It is necessary to perform this operation once to every RDRAM device in every tCCTRL interval in order to keep the IOL output current in its proper range. This example uses four COLX packets with a CAL command. These cause the RDRAM device to drive four calibration packets Q(a0) a time tCAC later. An offset of tRDTOCC must be placed between the Q(a0) packet and read data Q(a1) from the same device. These calibration packets are driven on the DQA4..3 and DQB4..3 wires. During current calibration the valu of DQA5 is undefined. The remaining DQA and DQB wires are not used during these calibration packets. The last COLX packet also contains a SAM command (concatenated with the CAL command). The RDRAM device samples the last calibration packet and adjusts its IOL current value. Unlike REF commands, CAL and SAM commands cannot be broadcast. This is because the calibration packets from different devices would interfere. Therefore, a current control transaction must be sent every tCCTRL /N, where N is the number of RDRAM devices on the Channel. The device field Da of the address a0 in the CAL/SAM command should be incremented after each transaction. Figure 25-2 shows an example of a temperature calibration sequence to the RDRAM device. This sequence is broadcast once every tTEMP interval to all the RDRAM devices on the Channel. The TCEN and TCAL are ROP commands, and cause the slew rate of the output drivers to adjust for temperature drift. During the quiet interval tTCQUIET the devices being calibrated can't be read, but they can be written. Figure 25-1 Current Control CAL/SAM Transaction Example
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T 20T 21 T 22 T 23 T 24T 25 T 26 T 27T 28T 29 T 30 T 31 T 32T 33 T 34 T 35 T 36T 37 T 38 T 39 T 40T 41 T 42 T 43T 44T 45 T 46 T 47
CTM/CFM ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0
Read data from the same device from an earlier RD command must be at this packet position or earier. Read data from a different device from an earlier RD command can be anywhere prior to the Q(a0) packet. Read data from a different device from a later RD command can be anywhere after to the Q(a0) packet. Read data from the same device from a later RD command must be at this packet position or later.
t CCTRL
CAL a0 CAL a0 CAL a0 CAL/SAM a0 CAL a2
t CAC
Q (a1) Q (a0)
t CCSAMTOREAD
Q (a1)
t READTOCC Transaction a0: CAL/SAM Transaction a1: RD Transaction a2: CAL/SAM
a0 = {Da, Bx} a1 = {Da, Bx} a2 = {Da, Bx}
DQA5 of the first calibrate packet has the inverted TSQ bit of INIT control register; i.e. logic 0 or high voltage means hot temperature. When used for monitoring, it should be enabled with the DQA3 bit (current control one value) in case there is no RDRAM present: HotTemp = /DQA5*DQA3 Note that DQB3 could be used instead of DQA3.
Figure 25-2 Temperature Calibration (TCEN-TCAL) Transactions to RDRAM
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12T 13 T 14 T 15 T 16T 17 T 18 T 19 T 20T 21 T 22 T 23 T 24T 25 T 26 T 27T 28T 29 T 30 T 31 T 32T 33 T 34 T 35 T 36T 37 T 38 T 39 T 40T 41 T 42 T 43T 44T 45 T 46 T 47
CTM/CFM t TEMP ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0
TCEN TCAL TCEN
t TCEN
tTCAL
t TCQUIET
CA L
Any ROW packet may be placed in the gap between the ROW packets with the TCEN and TCAL commands. No read data from devices being calibrated
54
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
26. Electrical Conditions
Electrical Conditions
Symbol Tj VDD, VDDa VDD,N,VDDa,N VDD,N,VDDa,N VCMOS Note1 Parameter and Conditions Junction temperature under bias Supply voltage Supply voltage droop (DC) during NAP interval (tNLIMT) Supply voltage ripple (AC) during NAP interval (tNLIMT) Supply voltage for CMOS pins (2.5V controllers) Supply voltage for CMOS pins (1.8V controllers) VTERM VREF VDIL Termination voltage Reference voltage RSL data input - low voltage tCYCLE=2.50ns tCYCLE=1.875ns VDIH RSL data input - high voltage
Note2
MIN. -- 2.50 - 0.13 -- -2.0 2.50 - 0.13 1.80 - 0.1 1.80 - 0.1 1.40 - 0.2 VREF - 0.5 VREF - 0.5 VREF + 0.2 VREF + 0.15 0.67 1.3 0.35 0.225 - 0.3 Note3 VCMOS / 2+0.25
MAX. 100 2.50 + 0.13 2.0 +2.0 2.50 + 0.25 1.80 + 0.2 1.80 + 0.1 1.40 + 0.2 VREF - 0.2 VREF - 0.15 VREF + 0.5 VREF + 0.5 1.00 1.8 1.00 1.00 + (VCMOS / 2- 0.25) VCMOS + 0.3
Note4
Unit C V % % V V V V V V V V V V V V V V
tCYCLE=2.50ns tCYCLE=1.875ns
RDA VCM VCIS, CTM VCIS, CFM VIL, CMOS VIH, CMOS
RSL input data asymmetry: RDA = (VDIH - VREF) / (VREF - VDIL) RSL clock input - common mode VCM = (VCIH + VCIL ) / 2 RSL clock input swing : VCIS = VCIH - VCIL (CTM, CTMN pins). RSL clock input swing : VCIS = VCIH - VCIL (CFM, CFMN pins). CMOS input low voltage CMOS input high voltage
Notes 1. VCMOS must remain on as long as VDD is applied and cannot be turned off. 2. VDIH is typically equal to VTERM (1.8V 0.1V) under DC conditions in a system. 3. Voltage undershoot is limited to -0.7V for a duration of less than 5ns. 4. Voltage overshoot is limited to VCMOS + 0.7V for a duration of less than 5ns.
Preliminary Data Sheet E0260E40 (Ver. 4.0)
55
EDR2518ABSE
27. Timing Conditions
Timing Conditions
Symbol tCYCLE Parameter CTM and CFM cycle times PC800 PC1066 tCR, tCF tCH, tCL tTR CTM and CFM input rise and fall times CTM and CFM high and low times CTM-CFM differential (MSE/MS=0/0) (MSE/MS=1/1) (MSE/MS=1/0) tDCW tDR, tDF tS, tH Domain crossing window DQA/DQB/ROW/COL input rise/fall times DQA/DQB/ROW/COL-to-CFM setup/hold time tDR1, tDF1 tDR2, tDF2 tCYCLE1 SIO0, SIO1 input rise and fall times CMD,SCK input rise and fall times SCK cycle time - Serial control register transactions SCK cycle time - Power transitions tCH1, tCL1 tS1 tH1 tS2 tH2 tS3 tH3 tS4 tH4 tNPQ tREADTOCC tCE tCD tFRM tNLIMIT tREF tCCTRL tTEMP tTCEN tTCAL tTCQUIET tPAUSE tBURST SCK high and low times tCYCLE=2.50ns tCYCLE=1.875ns tCYCLE=2.50ns tCYCLE=1.875ns CMD setup time to SCK rising or falling tCYCLE=2.50ns edge Note3 edge Note3 SIO0 setup time to SCK falling edge SIO0 hold time to SCK falling edge PDEV setup time on DQA5..0 to SCK rising edge PDEV hold time on DQA5..0 to SCK rising edge ROW2..0, COL4..0 setup time for quiet window ROW2..0, COL4..0 hold time for quiet window
Note4
MIN. 2.50 1.875 0.2 40% 0.0 0.9 -0.1 -0.1 tCYCLE=2.50ns tCYCLE=1.875ns tCYCLE=2.50ns tCYCLE=1.875ns 0.2 0.2 0.200 Note1,2 0.160 Note2 -- -- 1,000 10 7.5 4.25 3.5 1.25 1.0 1.0 1.0 40 40 0 5.5 -1 5 4 12 8 2 100 7 -- -- 34 tCYCLE -- 150 2 140 -- --
MAX. 3.33 2.5 0.5 60% 1.0 1.0 +0.1 +0.1 0.65 0.45 -- -- 5.0 2.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 10 32 100 ms 100 -- 2 -- 200 200
Unit ns
Figures
Figure 30-1
ns tCYCLE tCYCLE
Figure 30-1 Figure 30-1 Figure 22-1 Figure 30-1 Figure 30-1
tCYCLE ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE s ms -- ms tCYCLE tCYCLE tCYCLE s s
Figure 35-1 Figure 31-1
Figure 31-1
Figure 33-1 Figure 33-1 Figure 33-1 Figure 33-1
Figure 33-1
Figure 33-1
tCYCLE=1.875ns tCYCLE=1.875ns
CMD hold time to SCK rising or falling tCYCLE=2.50ns
Figure 33-1
Figure 33-1 Figure 33-1 Figure 23-4, 33-2 Figure 23-4, 33-2 Figure 23-4 Figure 23-4 Figure 23-3 Figure 25-1 Figure 25-1 Figure 23-4 Figure 23-3 Figure 23-2 Figure 23-1 Figure 24-1 Figure 25-1 Figure 25-2 Figure 25-2 Figure 25-2 Figure 25-2 Figure 22-1 Figure 24-2
Quiet on ROW / COL bits during NAP / PDN entry Offset between read data and CC packets (same device) CTM/CFM stable before NAP/PDN exit CTM/CFM stable after NAP/PDN entry ROW packet to COL packet ATTN framing delay Maximum time in NAP mode Refresh interval Current control interval Temperature control interval TCE command to TCAL command TCAL command to quiet window Quiet window (no read data) RDRAM delay (no RSL operations allowed) Interval after PDN or NAP (with self-refresh) exit in which all banks of the RDRAM must be refreshed at least once.
tCCSAMTOREAD Offset between CC packet and read data (same device)
56
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
Notes 1. This parameter also applies to a PC1066 part when operated with tCYCLE = 2.50ns. 2. tS,MIN and tH,MIN for other tCYCLE values can be interpolated between or extrapolated from the timings at the 2 specified tCYCLE values. 3. With VIL,CMOS = 0.5 VCMOS - 0.4 V and VIH,CMOS = 0.5 VCMOS + 0.4 V 4. Effective hold becomes tH4'=tH4 + [PDNXA * 64 * tSCYCLE + tPDNXB,MAX ] - [PDNX * 256 * tSCYCLE ] if [PDNX * 256 * tSCYCLE ] < [PDNXA * 64 * tSCYCLE + tPDNXB,MAX ]. See Figure 23-4.
Preliminary Data Sheet E0260E40 (Ver. 4.0)
57
EDR2518ABSE
28. Electrical Characteristics
Electrical Characteristics
Symbol JC IREF IOH IALL IOL rOUT IOL, NOM Parameter and Conditions Junction-to-Case thermal resistance VREF current @ VREF,MAX RSL output high current @ (0VOUT VDD) RSL IOL current @ VOL=0.9 V, VDD,MIN, Tj,MAX
Note1
MIN. -- -10 -10 tCYCLE=2.50ns tCYCLE=1.875ns 30.0 32.0 -- 150
Note2, 3
MAX. 0.5 +10 +10 90 90 2.0 -- 30.6 30.1 +10.0 0.3 --
Unit C/Watt A A mA mA mA mA mA A V V
RSL IOL current resolution step Dynamic output impedance RSL IOL current @ VOL=1.0 V tCYCLE=2.50ns tCYCLE=1.875ns
26.6 27.1 -10.0 -- VCMOS - 0.3
II,CMOS VOL,CMOS VOH,CMOS
CMOS input leakage current @ (0 VI,CMOS VCMOS) CMOS output low voltage @ IOL,CMOS = 1.0 mA CMOS output high voltage @ IOH,CMOS = - 0.25 mA
Note 1. This measurement is made in manual current control mode with all output device legs sinking current. 2. This measurement is made in automatic current control mode after at least 64 current control calibration operations to a device and after CCA and CCB are initialized to a value of 64. This value applies to all DQA and DQB pins. 3. This measurement is made in automatic current control mode with the ASYMA and ASYMB register fields set to 0.
29. Timing Characteristics
Timing Characteristics
Symbol tQ Parameter CTM-to-DQA/DQB output time tCYCLE = 2.50 ns tCYCLE = 1.875 ns tQR, tQF DQA/DQB output rise and fall times tCYCLE = 2.50 ns tCYCLE = 1.875 ns tQ1 tHR tQR1, tQF1 tPROP1 tNAPXA tNAPXB tPDNXA tPDNXB tAS tSA tASN tASP SCK-to-SIO0 delay @ CLOAD,MAX = 20 pF (SD read packet) SCK(pos)-to-SIO0 delay @ CLOAD,MAX = 20pF (SD read data hold) SIOOUT rise/fall @ CLOAD,MAX = 20 pF SIO0-to-SIO1 or SIO1-to-SIO0 delay @ CLOAD,MAX = 20 pF NAP exit delay - phase A NAP exit delay - phase B PDN exit delay - phase A PDN exit delay - phase B ATTN-to-STBY power state delay STBY-to-ATTN power state delay ATTN/STBY-to-NAP power state delay ATTN/STBY-to-PDN power state delay MIN. -0.260
Note1,2
MAX. +0.260
Note1,2
Unit ns
Figure(s)
Figure 32-1
-0.195 0.2 0.2 -- 2 -- -- -- -- -- -- -- -- -- --
Note2
+0.195
Note2
0.45 0.32 10 -- 12 20 50 40 4 9,000 1 0 8 8
ns
Figure 32-1
ns ns ns ns ns ns
Figure 34-1 Figure 34-1 Figure 34-1 Figure 34-1 Figure 23-4 Figure 23-4 Figure 23-4 Figure 23-4 Figure 23-2 Figure 23-2 Figure 23-3 Figure 23-3
s
tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE
Notes 1. This parameter also applies to a PC1066 part when operated with tCYCLE =2.50 ns. 2. tQ,MIN and tQ,MAX for other tCYCLE values can be interpolated between or extrapolated from the timings at the 2 specified tCYCLE values. 58
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
30. RSL Clocking
Figure 30-1 is a timing diagram which shows the detailed requirements for the RSL clock signals on the Channel. The CTM and CTMN are differential clock inputs used for transmitting information on the DQA and DQB, outputs. Most timing is measured relative to the points where they cross. The tCYCLE parameter is measured from the falling CTM edge to the falling CTM edge. The tCL and tCH parameters are measured from falling to rising and rising to falling edges of CTM. The tCR and tCF rise-and fall-time parameters are measured at the 20 % and 80 % points. The CFM and CFMN are differential clock outputs used for receiving information on the DQA, DQB, ROW and COL outputs. Most timing is measured relative to the points where they cross. The tCYCLE parameter is measured from the falling CFM edge to the falling CFM edge. The tCL and tCH parameters are measured from falling to rising and rising to falling edges of CFM. The tCR and tCF rise- and fall-time parameters are measured at the 20 % and 80 % points. The tTR parameters specifies the phase difference that may be tolerated with respect to the CTM and CFM differential clock inputs (the CTM pair is always earlier).
Figure 30-1 RSL Timing - Clock Signals
t CYCLE t CL CTM t CH t CR t CR V CIH 80% VCM 50% 20% CTMN t TR t CR CFM tCR V CIH 80% VCM 50% 20% CFMN t CL t CYCLE t CH t CF V CIL t CF t CF V CIL t CF
Preliminary Data Sheet E0260E40 (Ver. 4.0)
59
EDR2518ABSE
31. RSL - Receive Timing
Figure 31-1 is a timing diagram which shows the detailed requirements for the RSL input signals on the Channel. The DQA, DQB, ROW, and COL signals are inputs which receive information transmitted by a Direct RAC on the Channel. Each signal is sampled twice per tCYCLE interval. The set/hold window of the sample points is tS/tH. The sample points are centered at the 0 % and 50 % points of a cycle, measured relative to the crossing points of the falling CFM clock edge. The set and hold parameters are measured at the VREF voltage point of the input transition. The tDR and tDF rise- and fall-time parameters are measured at the 20 % and 80 % points of the input transition. Figure 31-1 RSL Timing - Data Signals for Receive
CFM
V CIH 80% VCM 50% 20%
CFMN 0.5*t CYCLE DQA DQB ROW COL even odd t DR tS tH tS tH
V CIL
V DIH 80% V REF 20% t DF VDIL
60
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
32. RSL - Transmit Timing
Figure 32-1 is a timing diagram which shows the detailed requirements for the RSL output signals on the Channel. The DQA and DQB signals are outputs to transmit information that is received by a Direct RAC on the Channel. Each signal is driven twice per tCYCLE interval. The beginning and end of the even transmit window is at the 75 % point of the previous cycle and at the 25 % point of the current cycle. The beginning and end of the odd transmit window is at the 25 % point and at the 75 % point of the current cycle. These transmit points are measured relative to the crossing points of the falling CTM clock edge. The size of the actual transmit window is less than the ideal tCYCLE/2, as indicated by the non-zero valued of tQ,MIN and tQ,MAX. The tQ parameters are measured at the 50 % voltage point of the output transition. The tQR and tQF rise- and fall-time parameters are measured at the 20 % and 80 % points of the output transition.
Figure 32-1 RSL Timing - Data Signals for Transmit
CTM
VCIH 80% VCM 50% 20%
CTMN
VCIL 0.75*t CYCLE 0.75*t CYCLE 0.25*t CYCLE
DQA DQB
tQR
tQ,MAX
t Q,MIN t Q,MAX
tQ,MIN VQH 80%
even
odd 50% 20%
t QF
VQL
Preliminary Data Sheet E0260E40 (Ver. 4.0)
61
EDR2518ABSE
33. CMOS - Receive Timing
Figure 33-1 is a timing diagram which shows the detailed requirements for the CMOS input signals. The CMD and SIO0 signals are inputs which receive information transmitted by a controller (or by another RDRAM DEVICE'Ss SIO1 output). SCK is the CMOS clock signal driven by the controller. All signals are high true. The cycle time, high phase time, and low phase time of the SCK clock are tCYCLE1, tCH1 and tCL1, all measured at the 50 % level. The rise and fall times of SCK, CMD, and SIO0 are tDR1 and tDF1, measured at the 20 % and 80 % levels. The CMD signal is sampled twice per tCYCLE1 interval, on the rising edge (odd data) and the falling edge (even data). The set/hold window of the sample points is tS1/tH1. The SCK and CMD timing points are measured at the 50 % level. The SIO0 signal is sampled once per tCYCLE1 interval on the falling edge. The set/hold window of the sample points is tS2/tH2. The SCK and SIO0 timing points are measured at the 50 % level.
Figure 33-1 CMOS Timing - Data Signals for Receive
t DR2 SCK V IH,CMOS 80% 50% 20% t CL1 t S1 tH1 tS1 t H1 V IH,CMOS 80% even odd 50% 20% t DF2 t DR1 SIO0 tS2 t H2 V IH,CMOS 80% 50% 20% t DF1 V IL,CMOS VIL,CMOS V IL,CMOS
t CYCLE1 t DF2 tDR2 CMD t CH1
62
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
The SCK clock is also used for sampling data on RSL input in one situation. Figure23-4 shows the PDN and NAP exit sequences. If the PSX field of the INIT register is one (Figure 22-1 control registers (1/7) "INIT Register"), then the PDN and NAP exit sequences are broadcast; i.e. all RDRAM devices that are in PDN or NAP will perform the exit sequence. If the PSX field of the INIT register is zero, then the PDN and NAP exit sequences are directed; i.e. only one RDRAM that is in PDN or NAP will perform the exit sequence. The address of that RDRAM is specified on the DQA[5:0] bus in the set hold window tS3/tH3 around the rising edge of SCK. This is shown Figure 33-2. The SCK timing point is measured at the 50 % level, and the DQA [5:0] bus signals are measured at the VREF level.
Figure 33-2 CMOS Timing - Device Address for NAP or PDN Exit
SCK
V IH,CMOS 80% 50% 20% V IL,CMOS t S3 t H3 V DIH 80% PDEV V REF 20% VDIL
DQA[5:0]
Preliminary Data Sheet E0260E40 (Ver. 4.0)
63
EDR2518ABSE
34. CMOS - Transmit Timing
Figure 34-1 is a timing diagram which shows the detailed requirements for the CMOS output signals. The SIO0 signal is driven once per tCYCLE1 interval on the falling edge. The clock-to-output window is tQ1,MIN /tQ1,MAX. The SCK and SIO0 timing points are measured at the 50 % level. The rise and fall times of SIO0 are tQR1 and tQF1, measured at the 20 % and 80 % levels. Figure34-1 also shows the combinational path connecting SIO0 to SIO1 and the path connecting SIO1 to SIO0 (read data only). The tPROP1 parameter specified this propagation delay. The rise and fall times of SIO0 and SIO1 input must be tDR1 and tDF1, measured at the 20 % and 80 % levels. The rise and fall times of SIO0 and SIO1 outputs are tQR1 and tQF1, measured at the 20 % and 80 % levels.
Figure 34-1 CMOS Timing - Data Signals for Transmit VIH,CMOS 80% 50% 20% t Q1,MAX t HR,MIN t QR1 SIO0 VOH,CMOS 80% 50% 20% t QF1 t DR1 SIO0 or SIO1 VIH,CMOS 80% 50% 20% VIL,CMOS t DF1 t PROP1,MAX t PROP1,MIN tQR1 VOH,CMOS SIO0 or SIO1 80% 50% 20% t QF1 VOL,CMOS VOL,CMOS VIL,CMOS
SCK
64
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
35. RSL - Domain Crossing Window
When read data is returned by the RDRAM device, information must cross from the receive clock domain (CFM) to the transmit clock domain (CTM). The tTR parameter permits the CFM to CTM phase to vary though an entire cycle ; i.e. there is no restriction on the alignment of these two clocks. A second parameter tDCW is needed in order to describe how the delay between a RD command packet and read data packet varies as a function of the tTR value. Figure 35-1 shows this timing for five distinct values of tTR. Case A (tTR=0) is what has been used throughout this document. The delay between the RD command and read data is tCAC. As tTR varies from zero to tCYCLE (cases A through E), the command to data delay is (tCAC-tTR). When the tTR value is in the range 0 to tDCW,MAX, the command to data delay can also be (tCAC-tTR-tCYCLE). This is shown as cases A' and B' (the gray packets). Similarly, when the tTR value is in the range (tCYCLE+tDCW,MIN) to tCYCLE, the command to data delay can also be (tCAC-tTR+tCYCLE). This is shown as cases D' and E' (the gray packets). The RDRAM device will work reliably with either the white or gray packet timing. The delay value is selected at initialization, and remains fixed thereafter.
Figure 35-1 RSL Timing - Crossing Read Domains
CFM COL
RDa1
***
t CYCLE
CTM DQA/B DQA/B
tTR Case A t TR=0
***
tCAC -t TR Q(a1) t CAC -tTR-tCYCLE Q(a1)
Case A' t TR=0
*** CTM DQA/B DQA/B
tTR Case B t TR =t DCW,MAX Case B' t TR =t DCW,MAX t CAC -t TR Q(a1) t CAC -t TR -t CYCLE Q(a1)
CTM DQA/B
tTR Case C t TR =0.5*t CYCLE
***
t CAC -t TR Q(a1)
CTM DQA/B DQA/B
t TR Case D tTR =t CYCLE + t DCW,MIN Case D' t TR =t CYCLE + t DCW,MIN
***
t CAC -tTR Q(a1) tCAC -t TR +t CYCLE Q(a1)
CTM
t TR
***
t CAC -t TR Case E t TR =t CYCLE Case E' t TR =tCYCLE t CAC -tTR+tCYCLE Q(a1) Q(a1)
DQA/B DQA/B
Preliminary Data Sheet E0260E40 (Ver. 4.0)
65
EDR2518ABSE
36. Timing Parameters
Timing Parameters Summary
Para- Description meter -AEP (-32P) 28 20 MIN. PC1066 -AE (-32) 28 20 -AD (-35) 32 22 PC800 -8C (-40) 28 20 MAX. Units Figures
tRC tRAS
Row Cycle time of RDRAM banks - the interval between ROWA packets with ACT commands to the same bank. RAS-asserted time of RDRAM bank - the interval between ROWA packet with ACT command and next ROWR packet with PRER Note 1 command to the same bank. Row Precharge time of RDRAM banks - the interval between ROWR packet with PRER Note 1 command and next ROWA packet with ACT command to the same bank. Precharge-to-precharge time of RDRAM device - the interval between successive ROWR packets with PRER Note 1 commands to any banks of the same device. RAS-to-RAS time of RDRAM device - the interval between successive ROWA packets with ACT commands to any banks of the same device. RAS-to-CAS Delay - the interval from ROWA packet with ACT command to COLC packet with RD or WR command. Note - the RAS-to-CAS delay seen by the RDRAM core (tRCDC) is equal to tRCD-C = 1 + tRCD because of differences in the row and column paths through the RDRAM interface. CAS Access delay - the interval from RD command to Q read data. The equation for tCAC is given in the TPARM register in Figure 22-1(5/7). CAS Write Delay - interval from WR command to D write data. CAS-to-CAS time of RDRAM bank - the interval between successive COLC commands.
--
tCYCLE Figure13-1 Figure14-1 tCYCLE Figure13-1 Figure14-1 tCYCLE Figure13-1 Figure14-1
Note 2
64s 8 8 10 8 --
tRP
tPP
8
8
8
8
--
tCYCLE Figure10-3
tRR
8
8
8
8
--
tCYCLE Figure12-1
tRCD
9
9
9
7
--
tCYCLE Figure13-1 Figure14-1
tCAC
8
9
9
8
12
tCYCLE Figure4-1
tCWD tCC
6 4 4 8
6 4 4 8
6 4 4 8
6 4 4 8
6 -- 4 --
tCYCLE Figure4-1 tCYCLE Figure13-1 Figure14-1 tCYCLE Figure2-1 tCYCLE Figure15-1
tPACKET Length of ROWA, ROWR, COLC, COLM or COLX packet. Interval from COLC packet with WR command to COLC tRTR packet which causes retire, and to COLM packet with bytemask. tOFFP The interval (offset) from COLC packet with RDA command, or from COLC packet with retire command (after WRA automatic precharge), or from COLC packet with PREC command, or from COLX packet with PREX command to the equivalent ROWR packet with PRER. The equation for tOFFP is given in the TPARM register in Figure 22-1(5/7). Interval from last COLC packet with RD command to ROWR packet with PRER. Interval from last COLC packet with automatic retire command to ROWR packet with PRER.
4
4
4
4
4
tCYCLE Figure14-2
tRDP tRTP
4 4
4 4
4 4
4 4
-- --
tCYCLE Figure13-1 tCYCLE Figure14-1
Notes 1. Or equivalent PREC or PREX command. See Figure 12-2. 2. This is a constraint imposed by the core, and is therefore in units of ms rather than tCYCLE.
66
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
37. Absolute Maximum Ratings
Absolute Maximum Ratings
Symbol VI,ABS VDD,ABS ,VDDa,ABS TSTORE Parameter Voltage applied to any RSL or CMOS pin with respect to GND Voltage on VDD and VDDa with respect to GND Storage temperature MIN. -0.3 -0.5 -50 MAX. VDD +0.3 VDD +1.0 +100 Unit V V C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
38. IDD - Supply Current Profile
IDD - Supply Current Profile
RDRAM Power Stated Steady-State Transaction RatesNote 1 Device in PDN. self-refresh enabled and INIT.LSR=0 Device in Nap. Device in STBY. This is the average for a device in STBY with (1) no packets on the channel, and (2) with packets sent to other devices. Device in ATTN. This is the average for a device in ATTN with (1) no packets on the channel, and (2) with packets sent to other devices. Device in ATTN. ACT command every 8*tCYCLE, PRE command every 8*tCYCLE, WR command every 4*tCYCLE and data is 1100..1100. Device in ATTN. ACT command every 8*tCYCLE, PRE command every 8*tCYCLE, RD command every 4*tCYCLE and data is 1111..1111 Note 2.
IDD value IDD,PDN IDD,NAP IDD,STBY
@ tCYCLE
2.50 ns/1.875 ns 2.50 ns/1.875 ns 2.50 ns 1.875 ns 2.50 ns 1.875 ns 2.50 ns 1.875 ns 2.50 ns 1.875 ns
MIN.
MAX. 6.0 4.0 70 90 100 130 530 680 520 660
Unit mA mA mA
IDD,ATTN
mA
IDD,ATTN-W
mA
IDD,ATTN-R
mA
Notes 1. The CMOS interface consumes power in all power states. 2. This does not include the IOL sink current. The RDRAM device dissipates IOL*VOL in each output driver when a logic one is driven.
Preliminary Data Sheet E0260E40 (Ver. 4.0)
67
EDR2518ABSE
39. Capacitance and Inductance
Figure 39-1 shows the equivalent load circuit of the RSL and CMOS pins. The circuit models the load that the device presents to the Channel. This circuit does not include pin coupling effects that are often present in the packaged device. Because coupling effects make the effective single-pin inductance LI, and capacitance CI, a function of neighboring pins, these parameters are intrinsically data-dependent. For purposes of specifying the device electrical loading on the Channel, the effective LI and CI are defined as the worst-case values over all specified operating conditions. LI is defined as the effective pin inductance based on the device pin assignment. Because the pad assignment places each RSL signal adjacent to an AC ground (a GND or VDD pin), the effective inductance must be defined based on this configuration. Therefore, LI assumes a loop with the RSL pin adjacent to an AC ground. CI is defined as the effective pin capacitance based on the device pin assignment. It is the sum of the effective package pin capacitance and the IO pad capacitance. Figure 39-1 Equivalent Load Circuit for RSL Pins
Pad
LI DQA,DQB,RQ Pin CI RI GND Pin
Pad
LI
CTM,CTMN, CFM,CFMN Pin
CI RI GND Pin
Pad
L I,CMOS SCK,CMD Pin CI
GND Pin
Pad
L I,CMOS SIO0,SIO1 Pin C I,CMOS,SIO
GND Pin
68
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
RSL Pin Parasitics
Symbol LI Parameter and Conditions - RSL pins RSL effective input inductance 1066 MHz 800 MHz L12 LI CI Mutual inductance between any DQA or DQB RSL signals. Mutual inductance between any ROW or COL RSL signals. Difference in LI value between any RSL pins of a single device. RSL effective input capacitance
Note
MIN. - - - - - 2.0 2.0 - - 4 4
MAX. 3.5 4.0 0.2 0.6 1.8 2.3 2.4 0.1 0.06 10 15
Unit pF
nH nH nH pF
1066 MHz 800 MHz
C12 CI RI
Mutual capacitance between any RSL signals. Difference in CI value between any RSL pins of a single device. RSL effective input resistance 1066 MHz 800 MHz
pF pF
Note This value is a combination of the device IO circuitry and package capacitances measured at VDD = 2.5 V and f = 400 MHz with pin based at 1.4 V.
CMOS Pin Parasitics
Symbol LI,CMOS CI,CMOS CI,CMOS,SIO Parameter and Conditions - CMOS pins CMOS effective input inductance CMOS effective input capacitance (SCK,CMD) CMOS effective input capacitance (SIO1,SIO0)
Note Note
MIN. - 1.7 -
MAX. 8.0 2.1 7.0
Unit nH pF pF
Note This value is a combination of the device IO circuitry and package capacitances.
Preliminary Data Sheet E0260E40 (Ver. 4.0)
69
EDR2518ABSE
40. Interleaved Device Mode
Interleaved Device Mode permits a group of eight RDRAM devices on the Channel to collectively respond to acommand. The purpose of this collective response is to limit the number of bits in each dualoct data packet which are read from or written to a single RDRAM device device. This capability permits a memory controller to implement hardware for fault detection and correction that can tolerate the complete internal failure of one RDRAM device on a Channel. The IDM bit of the INIT control register enables this fault tolerant operating mode. When it is set, the RDRAM device will interpret the DR4..0 and DC4..0 fields of the ROW and COLC packets differently. Figure 40-1 shows the differences using an example system with eight RDRAM devices. The DEVID4..0 registers of these RDRAM devices are initial-ized to "00000" through "00111'. However, when the IDM bit is set, only the upper two bits (DEVID4..3) will be compared to the DR4..3 and DC4..3 fields. This means that ROW and COLC packets will be executed by groups of eight RDRAM devices, with a Channel containing from one to four of these groups. The low-order DR2..0 bits are not used when IDM is set, and the low-order DC2..0 bits have a modified function described below. With IDM set, a directed ACT or PRE command in a ROW packet causes eight RDRAM devices to perform the indicated operation. Likewise, when a RD or WR command is specified in a COLC command, the selected group of eight RDRAM devices responds. When using IDM, devices must be added to the Channel in groups of eight. An application will typically make the IDM bit setting the same for all RDRAM devices on a Channel. The mechanism for indicating a broadcast ROW packet (DR4F and DR4T are both set to one) is not affected by the setting of the IDM bit; i.e. IDM mode does not change the broadcast ROW packet mechanism. Likewise, the COLX fields (DX4..0, XOP4..0, and BX5..0) are not changed by IDM mode - all COLX packets are directed to a single device. When the IDM bit is set, COLM packets should not be used (the M bit should be set to zero, selecting only COLX packets). This is because the mapping of bytes to RDRAM device storage cells is changed by IDM mode. Returning to Figure 40-1, the remaining fields of the ROW and COLC packets are interpreted in the same way regardless of the setting of the IDM bit - IDM mode does not affect these fields. Specifically, the BR5..0 and BC5..0 fields of the ROW and COLC packets are used to select one of the banks just as when IDM is not set. The R8..0 field of the ROW packet selects a row of the selected (BR5..0) bank to load into the bank's sense amp. And the C6..0 field selects one dualoct of the selected (BC5..0) bank's sense amp. The IDM bit affects what is done with this selected dualoct. When IDM is not set, the dualoct is driven onto the Channel by the single selected RDRAM device. When IDM is set, each RDRAM device of the eight device group selected by DC4..3 drives 16 or 24 bits (x18 device) of the 144-bit dualoct. The bits driven are a function of the DEVID2..0 RDRAM register field, the DC2..0 COLC packet field, and the device width (x18). Figure 40-1 shows the mapping that is appropriate for DC2..0=000. Figure 40-2 and Figure 40-3 show the mapping for all eight values of DC2..0. There are eight mappings, which are rotated among the eight devices using the following equation: Pin = 7 - 4 * (DEVID2^DC2) - 2 * (DEVID1^DC1) - 1 * (DEVID0^DC0) (Eq 1) where "^" is the exclusive-or function. "Pin" is the pin number that is driven by the RDRAM device with the DEVID2..0 value. For example, Pin=0 means the RDRAM drives DQA0 and DQB0, and so forth. The DQA8 pin is always driven with DQA7, and DQB8 is always driven with DQB6 for x18 devices. For x16 devices, the DQA8 and DQB8 pins are not used. For each of the eight mappings, the eight-RDRAM group supplies a complete dualoct. As the application steps through eight values of DC2..0, all the bits of the eight underlying dualocts will be accessed. Thus, an eight-RDRAM group appears to be a single RDRAM device with eight times the normal page size, with the DC2..0 field providing the extra column addressing informa-tion (beyond what C6..0 provides).
70
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
Figure 40-1 ACT, PRE, RD, and WR Commands for Eight RDRAM System with IDM = 1
RDRAM 0 DEVID 4..0 00000 RDRAM 1 00001 RDRAM 2 00010 RDRAM 3 00011 RDRAM 4 00100 RDRAM 5 00101 RDRAM 6 00110 RDRAM 7 00111
DR4..3 DC4..3 access device
compare to DEVID4..3
bank array BR5..0 BC5..0
* *
*
access bank
*
same as device 0 one bank
**
same as device 0
same as device 0
same as device 0
same as device 0
same as device 0
same as device 0
R12..0
**
*
access row
**
*
PRE
ACT
C6..0
**
sense amp.
**
access column WR RD
DC2..0 =000 form dualoct
DQA7 DQB7 DQA8 Channel
DQA6 DQB6 DQB8
DQA5 DQB5
DQA4 DQB4
DQA3 DQB3
DQA2 DQB2
DQA1 DQB1
DQA0 DQB0
DQA0
**
notation
* DQA8 DQB0
*
* * ** * *
* DQB8 CTM/CFM
*
**
**
device (2 banks)
B
bank (2 rows)
R
row (2C dualocts)
dualoct (144 bits)
one bit
Preliminary Data Sheet E0260E40 (Ver. 4.0)
71
EDR2518ABSE
Figure 40-2 Mapping from DEVID2..0 and DC2..0 Fields to DQ Packet with IDM = 1
DEVID2..0 000 DC2..0 001 010 011 100 101 110 111
Mapping for previous figure 000
DQA7 DQB7 DQA8
DQA6 DQB6 DQB8
DQA5 DQB5
DQA4 DQB4
DQA3 DQB3
DQA2 DQB2
DQA1 DQB1
DQA0 DQB0
001
CTM/CFM DQA0 DQA1 DQA2 DQA3 DQA4 DQA5 DQA6 DQA7 DQA8 DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8
DQA6 DQB6 DQB8
DQA7 DQB7 DQA8
DQA4 DQB4
DQA5 DQB5
DQA2 DQB2
DQA3 DQB3
DQA0 DQB0
DQA1 DQB1
010
DQA5 DQB5
DQA4 DQB4
DQA7 DQB7 DQA8
DQA6 DQB6 DQB8
DQA1 DQB1
DQA0 DQB0
DQA3 DQB3
DQA2 DQB2
011
DQA4 DQB4
DQA5 DQB5
DQA6 DQB6 DQB8
DQA7 DQB7 DQA8
DQA0 DQB0
DQA1 DQB1
DQA2 DQB2
DQA3 DQB3
72
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
Figure 40-3 Mapping from DEVID2..0 and DC2..0 Fields to DQ Packet with IDM = 1 (continued)
DEVID2..0 000 DC2..0 001 010 011 100 101 110 111
100
DQA3 DQB3
DQA2 DQB2
DQA1 DQB1
DQA0 DQB0
DQA7 DQB7 DQA8
DQA6 DQB6 DQB8
DQA5 DQB5
DQA4 DQB4
101
CTM/CFM DQA0 DQA1 DQA2 DQA3 DQA4 DQA5 DQA6 DQA7 DQA8 DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8
DQA2 DQB2
DQA3 DQB3
DQA0 DQB0
DQA1 DQB1
DQA6 DQB6 DQB8
DQA7 DQB7 DQA8
DQA4 DQB4
DQA5 DQB5
110
DQA1 DQB1
DQA0 DQB0
DQA3 DQB3
DQA2 DQB2
DQA5 DQB5
DQA4 DQB4
DQA7 DQB7 DQA8
DQA6 DQB6 DQB8
111
DQA0 DQB0
DQA1 DQB1
DQA2 DQB2
DQA3 DQB3
DQA4 DQB4
DQA5 DQB5
DQA6 DQB6 DQB8
DQA7 DQB7 DQA8
Preliminary Data Sheet E0260E40 (Ver. 4.0)
73
EDR2518ABSE
41. Glossary of Terms
ACT activate activate adjacent Activate command from AV field. To access a roe and place in sense amp. To access a row and place in sense amp. Two RDRAM banks which share sense amps (also called doubled banks). CCA register field for RSL VOL / VOH. Power state - ready for ROW / COL packets. Power state - transmitting Q packets. Power state - receiving D packets. Opcode field in ROW packets. A block of 2RBIT*2CBIT storage cells in the core of the RDRAM. Bank address field in CLC packet. CNFGA register field - # bank address bits. An operation executed by all RDRAM devices. Bank address field in ROW packets. Idle cycle(s) on RDRAM pins needed because of a resource constraint. CNFGB register field - 9 bits per byte. Bank address field in COLX packet. Column address field in COLC packet. Calibrate (IOL) command in XOP field. CNFGB register field - # column address bits. Control register - current control A. Control register - current control B. Clock pins for receiving packets. ROW / COL / DQ pins and external wires. Clear reset command from SOP field. CMOS pins for initialization / power control. Control register with configuration fields. Control register with configuration fields. Pins for column-access control. Column operation packet on COL pins. Write mask packet on COL pins. Rows in a bank or activated in sense amps have 2CBTI dualocts column storage. A decoded bit-combination from a field. Extended operation packet on COL pins. A logic-device which drives the ROW / COL / DQ wires for a Channel of RDRAM devices. Column opcode field in COLC packet. The banks and sense amps of an RDRAM. Clock pins for transmitting packets. Periodic operations to update the proper IOL Value of RSL output drivers. LSR M MA MB MSK MVER NAP NAPR NAPRC NAPXA NAPXB NOCOP NOROP NOXOP NSR packet PDN PDNR PDNXA PDNXB pin efficiency PRE PREC precharge PRER DM Doubled-bank DQ DQA DQB DQS D DBL DC device DEVID Write data packet on DQ pins. CNFGB register field - doubled-bank. Device address field in COLC packet. An RDRAM on a Channel. Control register with device address that is matched against DR, DC, and DX fields. Device match for ROW packet decode. RDRAM with shared sense amp. DQA and DQB pins. Pins for data byte A. Pins for data byte B. NAPX register field - PDN/NAP exit.
ASYM ATTN ATTNR ATTNW AV bank
BC BBIT broadcast BR bubble
DR,DR4T,DR4F Device address field and packet framing fields in ROW and ROWE packets. dualoct DX field INIT initialization 16 bytes - the smallest addressable datum. Device address field in COLX packet. A collection of bits in a packet. Control register with initialization fields. Configuring a Channel of RDRAM devices so they are ready to respond to transactions. CNFGA register field - low-power self-refresh. Mask opcode field (COLM/COLX packet). Field in COLM packet for masking byte A. Field in COLM packet for masking byte B. Mask command in M field. Control register - manufacturer ID. Power state - needs SCK/CMD wakeup. Nap command in ROP field. Conditional nap command in ROP field. NAPX register field - NAP exit delay A. NAPX register field - NAP exit delay B. No-operation command in COP field. No-operation command in ROP field. No-operation command in XOP field. INIT register field - NAP self-refresh. A collection of bits carried on the Channel. Power state - needs SCK/CMD wakeup. Powerdown command in ROP field. Control register - PDN exit delay A. Control register - PDN exit delay B. The fraction of non-idle cycles on a pin. PREC, PRER, PREX precharge commands. Precharge command in COP field. Prepares sense amp and bank for activate. Precharge command in ROP field.
BYT BX C CAL CBIT CCA CCB CFM,CFMN Channel CLRR CMD CNFGA CNFGB COL COLC COLM column
Command COLX controller
COP core CTM, CTMN Current control
74
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
PREX PSX PSR PVER Q R RBIT RD/RDA read receive
Precharge command in XOP field. INIT register field - PDN/NAP exit. INIT register field - PDN self-refresh. CNFGB register field - protocol version. Read data packet on DQ pins. Row address field of ROWA packet. CNFGB register field - #row address bits. Read (/precharge) command in COP field. Operation of accessing sense amp data. Moving information from the Channel into the RDRAM (a serial stream is demuxed). Refresh-activate command in ROP field. Control register - next bank (self-refresh). CNFGA register field - ignore bank bits (for REFA and self-refresh). Refresh-precharge command in ROP field. Control register - next row for REFA. Periodic operations to restore storage cells. The automatic operation that stores write buffer into sense amp after WR command. RLXC, RLXR, RLXX relax commands. Relax command in COP field. Relax command in ROP field. Relax command in XOP field. Row-opcode field in ROWR packet. 2CBIT dualocts of cells (bank/sense amp). Pins for row-access control ROWA or ROWR packets on ROW pins. Activate packet on ROW pins. Row operation packet on ROW pins. Alternate name for ROW/COL pins. Rambus Signal levels. Sample (IOL) command in XOP field. Serial address packet for control register transactions w/ SA address field. Serial broadcast field in SRQ. CMOS clock pin. Serial data packet for control register transactions w/ SD data field. Serial device address in SRQ packet. INIT register field - Serial device ID. Refresh mode for PDN and NAP. Fast storage that holds copy of bank's row.
SETF SETR SINT
Set fast clock command from SOP field. Set reset command from SOP field. Serial interval packet for control register read/write transactions. CMOS serial pins for control registers. Serial opcode field in SRQ. Serial read opcode command from SOP. INIT register field - Serial repeat bit. Serial request packet for control register read/write transactions. Power state - ready for ROW packets. Control register - stepping version. Serial write opcode command from SOP. TCLSCAS register field - tCAS core delay. TCLSCAS register field - tCLS core delay. Control register - tCAS and tCLS delay. Control register - tCYCLE delay. Control register - tDAC delay. Control register - for test purposes. Control register - for test purposes. Control register - tRDLY delay. ROW, COL, DQ packets for memory access. Moving information from the RDRAM onto the Channel (parallel word is muxed). Write (/precharge) command in COP field. Operation of modifying sense amp data. Extended opcode field in COLX packet.
SIO0,SIO1 SOP SRD SRP SRQ
STBY SVER SWR TCAS TCLS TCLSCAS TCYCLE TDAT TEST77 TEST78 TRDLY transaction transmit
REFA REFB REFBIT
REFP REFR refresh retire
RLX RLXC RLXR RLXX ROP row ROW ROW ROWA ROWR RQ RSL SAM SA
WR/WRA write XOP
SBC SCK SD
SDEV SDEVID self-refresh sense amp
Preliminary Data Sheet E0260E40 (Ver. 4.0)
75
EDR2518ABSE
42. Package Drawing
80-ball FBGA (BGA) EDR2518ABSE: Sn-Pb solder ball EDR2518ABSE-E: Lead free solder ball (Sn-Ag-Cu)
Unit: mm
0.2 S A
10.2 0.1
INDEX MARK
0.2 S B
17.16 0.10
0.2 S
1.13 max.
S 0.1 S
0.35 0.05
1.2 1.9
0.8 1.1 1.78
B
0.8
A
0.4
80-0.45 0.05 INDEX MARK
0.08 M S A B
ECA-TS2-0089-01
76
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
43. Recommended Soldering Conditions
Please consult our sales office for soldering conditions of the EDR2518ABSE. Type of Surface Mount Device EDR2518ABSE: 80-ball FBGA ( BGA) < Sn-Pb >, EDR2518ABSE-E: 80-ball FBGA ( BGA) < Lead free (Sn-Ag-Cu) >
Preliminary Data Sheet E0260E40 (Ver. 4.0)
77
EDR2518ABSE
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
78
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
Rambus, RDRAM and the Rambus logo are registered trademarks of Rambus Inc. Direct Rambus, Direct RDRAM, RIMM, SO-RIMM and QRSL are trademarks of Rambus Inc.
BGA is a registered trademark of Tessera, Inc.
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0107

▲Up To Search▲

Price & Availability of EDR2518ABSE-AEP-E

	To Download EDR2518ABSE-AEP-E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .